Search

Gary Chin

Examiner (ID: 1842)

Most Active Art Unit
2304
Art Unit(s)
2306, 2304, 2307, 3661, 2763, 3614, 2203
Total Applications
2057
Issued Applications
1788
Pending Applications
41
Abandoned Applications
228

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16873272 [patent_doc_number] => 20210166739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => SEMICONDUCTOR MEMORY DEVICE WITH POWER GATING CIRCUIT FOR DATA INPUT/OUTPUT CONTROL BLOCK AND DATA INPUT/OUTPUT BLOCK AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/174527 [patent_app_country] => US [patent_app_date] => 2021-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7632 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17174527 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/174527
Semiconductor memory device with power gating circuit for data input/output control block and data input/output block and semiconductor system including the same Feb 11, 2021 Issued
Array ( [id] => 16888650 [patent_doc_number] => 20210174847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => SEMICONDUCTOR MEMORY DEVICE WITH POWER GATING CIRCUIT FOR DATA INPUT/OUTPUT CONTROL BLOCK AND DATA INPUT/OUTPUT BLOCK AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/174569 [patent_app_country] => US [patent_app_date] => 2021-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7629 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17174569 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/174569
Semiconductor memory device with power gating circuit for data input/output control block and data input/output block and semiconductor system including the same Feb 11, 2021 Issued
Array ( [id] => 19213429 [patent_doc_number] => 12002501 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-04 [patent_title] => Apparatuses and methods for distributed targeted refresh operations [patent_app_type] => utility [patent_app_number] => 17/175485 [patent_app_country] => US [patent_app_date] => 2021-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9273 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17175485 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/175485
Apparatuses and methods for distributed targeted refresh operations Feb 11, 2021 Issued
Array ( [id] => 16858117 [patent_doc_number] => 20210158862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => APPARATUS WITH A ROW-HAMMER ADDRESS LATCH MECHANISM [patent_app_type] => utility [patent_app_number] => 17/168049 [patent_app_country] => US [patent_app_date] => 2021-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11120 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17168049 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/168049
Apparatus with a row-hammer address latch mechanism Feb 3, 2021 Issued
Array ( [id] => 17173810 [patent_doc_number] => 20210327481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => SEMICONDUCTOR STORING APPARATUS AND READOUT METHOD [patent_app_type] => utility [patent_app_number] => 17/165945 [patent_app_country] => US [patent_app_date] => 2021-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5113 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17165945 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/165945
Semiconductor storing apparatus including multiple chips and continous readout method Feb 2, 2021 Issued
Array ( [id] => 17606909 [patent_doc_number] => 11335401 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-17 [patent_title] => Memory unit with multiple word lines for nonvolatile computing-in-memory applications and current calibrating method thereof [patent_app_type] => utility [patent_app_number] => 17/161618 [patent_app_country] => US [patent_app_date] => 2021-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4613 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17161618 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/161618
Memory unit with multiple word lines for nonvolatile computing-in-memory applications and current calibrating method thereof Jan 27, 2021 Issued
Array ( [id] => 17010651 [patent_doc_number] => 20210241812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => MEMORY SYSTEM AND SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/160885 [patent_app_country] => US [patent_app_date] => 2021-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6122 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17160885 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/160885
Memory system and semiconductor storage device configured to discharge word line during abrupt power interrupt Jan 27, 2021 Issued
Array ( [id] => 17010647 [patent_doc_number] => 20210241808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/158301 [patent_app_country] => US [patent_app_date] => 2021-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 32316 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17158301 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/158301
Semiconductor device for detecting failure in address decoder Jan 25, 2021 Issued
Array ( [id] => 18016154 [patent_doc_number] => 11508458 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Access schemes for access line faults in a memory device [patent_app_type] => utility [patent_app_number] => 17/150902 [patent_app_country] => US [patent_app_date] => 2021-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 36888 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17150902 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/150902
Access schemes for access line faults in a memory device Jan 14, 2021 Issued
Array ( [id] => 17737758 [patent_doc_number] => 20220223220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => MEMORY DEVICE AND METHOF FOR ERROR DETECTION [patent_app_type] => utility [patent_app_number] => 17/148535 [patent_app_country] => US [patent_app_date] => 2021-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5108 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17148535 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/148535
Memory device and method for error detection Jan 12, 2021 Issued
Array ( [id] => 17558927 [patent_doc_number] => 11315646 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-26 [patent_title] => Memory device having improved data reliability by varying program sequences [patent_app_type] => utility [patent_app_number] => 17/141408 [patent_app_country] => US [patent_app_date] => 2021-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 10827 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17141408 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/141408
Memory device having improved data reliability by varying program sequences Jan 4, 2021 Issued
Array ( [id] => 17723172 [patent_doc_number] => 20220215894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => REFERENCE VOLTAGE ADJUSTMENT BASED ON POST-DECODING AND PRE-DECODING STATE INFORMATION [patent_app_type] => utility [patent_app_number] => 17/140472 [patent_app_country] => US [patent_app_date] => 2021-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9999 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17140472 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/140472
Reference voltage adjustment based on post-decoding and pre-decoding state information Jan 3, 2021 Issued
Array ( [id] => 16904526 [patent_doc_number] => 20210183442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => NON-VOLATILE MEMORY DEVICE INCLUDING A ROW DECODER WITH A PULL-UP STAGE [patent_app_type] => utility [patent_app_number] => 17/123518 [patent_app_country] => US [patent_app_date] => 2020-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9235 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17123518 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/123518
Non-volatile memory device including a row decoder with a pull-up stage controlled by a current mirror Dec 15, 2020 Issued
Array ( [id] => 17277646 [patent_doc_number] => 20210383844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => MEMORY DEVICE INCLUDING VARIABLE REFERENCE RESISTOR AND METHOD OF CALIBRATING THE VARIABLE REFERENCE RESISTOR [patent_app_type] => utility [patent_app_number] => 17/120405 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9357 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17120405 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/120405
Memory device including variable reference resistor and method of calibrating the variable reference resistor Dec 13, 2020 Issued
Array ( [id] => 17660448 [patent_doc_number] => 20220180913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => MIDPOINT SENSING REFERENCE GENERATION FOR STT-MRAM [patent_app_type] => utility [patent_app_number] => 17/113595 [patent_app_country] => US [patent_app_date] => 2020-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6159 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17113595 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/113595
Midpoint sensing reference generation for STT-MRAM Dec 6, 2020 Issued
Array ( [id] => 16873291 [patent_doc_number] => 20210166758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => ENERGY RECOVERY IN FILAMENTARY RESISTIVE MEMORIES [patent_app_type] => utility [patent_app_number] => 17/108737 [patent_app_country] => US [patent_app_date] => 2020-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8368 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17108737 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/108737
Energy recovery in filamentary resistive memories Nov 30, 2020 Issued
Array ( [id] => 17908431 [patent_doc_number] => 11462291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-04 [patent_title] => Apparatuses and methods for tracking word line accesses [patent_app_type] => utility [patent_app_number] => 17/102266 [patent_app_country] => US [patent_app_date] => 2020-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 13199 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17102266 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/102266
Apparatuses and methods for tracking word line accesses Nov 22, 2020 Issued
Array ( [id] => 17971115 [patent_doc_number] => 11488662 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Concurrent multi-bit access in cross-point array [patent_app_type] => utility [patent_app_number] => 17/099030 [patent_app_country] => US [patent_app_date] => 2020-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 30 [patent_no_of_words] => 22649 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17099030 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/099030
Concurrent multi-bit access in cross-point array Nov 15, 2020 Issued
Array ( [id] => 17787844 [patent_doc_number] => 11410980 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => Integrated assemblies comprising vertically-stacked decks [patent_app_type] => utility [patent_app_number] => 17/086908 [patent_app_country] => US [patent_app_date] => 2020-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7960 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17086908 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/086908
Integrated assemblies comprising vertically-stacked decks Nov 1, 2020 Issued
Array ( [id] => 16624593 [patent_doc_number] => 20210043246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => SYSTEMS AND METHODS FOR MAINTAINING REFRESH OPERATIONS OF MEMORY BANKS USING A SHARED ADDRESS PATH [patent_app_type] => utility [patent_app_number] => 17/083951 [patent_app_country] => US [patent_app_date] => 2020-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15712 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17083951 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/083951
Systems and methods for maintaining refresh operations of memory banks using a shared address path Oct 28, 2020 Issued
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