Search

Gary Chin

Examiner (ID: 1842)

Most Active Art Unit
2304
Art Unit(s)
2306, 2304, 2307, 3661, 2763, 3614, 2203
Total Applications
2057
Issued Applications
1788
Pending Applications
41
Abandoned Applications
228

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16487464 [patent_doc_number] => 20200381073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => METHOD FOR DRIVING AN ELECTRONIC DEVICE INCLUDING A SEMICONDUCTOR MEMORY IN A TEST MODE [patent_app_type] => utility [patent_app_number] => 16/997652 [patent_app_country] => US [patent_app_date] => 2020-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12795 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16997652 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/997652
Method for driving an electronic device including a semiconductor memory in a test mode Aug 18, 2020 Issued
Array ( [id] => 17606911 [patent_doc_number] => 11335403 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-17 [patent_title] => Techniques for programming multi-level self-selecting memory cell [patent_app_type] => utility [patent_app_number] => 16/983486 [patent_app_country] => US [patent_app_date] => 2020-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 14115 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16983486 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/983486
Techniques for programming multi-level self-selecting memory cell Aug 2, 2020 Issued
Array ( [id] => 17047773 [patent_doc_number] => 11100962 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Semiconductor device with a power-down mode and a power gating circuit and semiconductor system including the same [patent_app_type] => utility [patent_app_number] => 16/943874 [patent_app_country] => US [patent_app_date] => 2020-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 26 [patent_no_of_words] => 13298 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16943874 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/943874
Semiconductor device with a power-down mode and a power gating circuit and semiconductor system including the same Jul 29, 2020 Issued
Array ( [id] => 16440140 [patent_doc_number] => 20200357467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => APPARATUSES AND METHODS FOR COMPARING DATA PATTERNS IN MEMORY [patent_app_type] => utility [patent_app_number] => 16/939919 [patent_app_country] => US [patent_app_date] => 2020-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24896 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16939919 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/939919
Apparatuses and methods for comparing data patterns in memory Jul 26, 2020 Issued
Array ( [id] => 16424822 [patent_doc_number] => 20200350020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => MEMORY DEVICE HAVING IMPROVED DATA RELIABILITY AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/935598 [patent_app_country] => US [patent_app_date] => 2020-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13137 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16935598 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/935598
Three-dimensional NAND flash memory device having improved data reliability by varying program intervals, and method of operating the same Jul 21, 2020 Issued
Array ( [id] => 16394220 [patent_doc_number] => 20200335161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-22 [patent_title] => MEMRISTIVE DEVICE AND METHOD BASED ON ION MIGRATION OVER ONE OR MORE NANOWIRES [patent_app_type] => utility [patent_app_number] => 16/922786 [patent_app_country] => US [patent_app_date] => 2020-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9221 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16922786 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/922786
Memristive device and method based on ion migration over one or more nanowires Jul 6, 2020 Issued
Array ( [id] => 16780421 [patent_doc_number] => 20210117500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => METHODS TO TOLERATE PROGRAMMING AND RETENTION ERRORS OF CROSSBAR MEMORY ARRAYS [patent_app_type] => utility [patent_app_number] => 16/912717 [patent_app_country] => US [patent_app_date] => 2020-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13316 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16912717 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/912717
METHODS TO TOLERATE PROGRAMMING AND RETENTION ERRORS OF CROSSBAR MEMORY ARRAYS Jun 25, 2020 Abandoned
Array ( [id] => 16730909 [patent_doc_number] => 20210098057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => SRAM LOW-POWER WRITE DRIVER [patent_app_type] => utility [patent_app_number] => 16/911313 [patent_app_country] => US [patent_app_date] => 2020-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5068 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16911313 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/911313
SRAM LOW-POWER WRITE DRIVER Jun 23, 2020 Abandoned
Array ( [id] => 17283889 [patent_doc_number] => 11200929 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-12-14 [patent_title] => Time division multiplexing (TDM) based optical ternary content addressable memory (TCAM) [patent_app_type] => utility [patent_app_number] => 16/905694 [patent_app_country] => US [patent_app_date] => 2020-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 16603 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16905694 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/905694
Time division multiplexing (TDM) based optical ternary content addressable memory (TCAM) Jun 17, 2020 Issued
Array ( [id] => 17295156 [patent_doc_number] => 20210390995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-16 [patent_title] => Locally Timed Sensing of Memory Device [patent_app_type] => utility [patent_app_number] => 16/900470 [patent_app_country] => US [patent_app_date] => 2020-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4590 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16900470 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/900470
Locally timed sensing of memory device Jun 11, 2020 Issued
Array ( [id] => 16347763 [patent_doc_number] => 20200312414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => MULTI-PASS PROGRAMMING PROCESS FOR MEMORY DEVICE WHICH OMITS VERIFY TEST IN FIRST PROGRAM PASS [patent_app_type] => utility [patent_app_number] => 16/900015 [patent_app_country] => US [patent_app_date] => 2020-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23326 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16900015 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/900015
Multi-pass programming process for memory device which omits verify test in first program pass Jun 11, 2020 Issued
Array ( [id] => 16691853 [patent_doc_number] => 20210074332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => MEMORY SYSTEM STORAGE DEVICE WITH PATH CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/877752 [patent_app_country] => US [patent_app_date] => 2020-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11327 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16877752 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/877752
Memory system storage device including path circuit in parallel with auxiliary power device May 18, 2020 Issued
Array ( [id] => 16285992 [patent_doc_number] => 20200279594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-03 [patent_title] => DYNAMIC RANDOM ACCESS MEMORY ARRAY, SEMICONDUCTOR LAYOUT STRUCTURE AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/878481 [patent_app_country] => US [patent_app_date] => 2020-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9110 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16878481 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/878481
Dynamic random access memory array, semiconductor layout structure and fabrication method thereof May 18, 2020 Issued
Array ( [id] => 18331645 [patent_doc_number] => 11636895 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-25 [patent_title] => Non-volatile resistive memory device including a plurality of write modes [patent_app_type] => utility [patent_app_number] => 16/870506 [patent_app_country] => US [patent_app_date] => 2020-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 42 [patent_no_of_words] => 13479 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16870506 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/870506
Non-volatile resistive memory device including a plurality of write modes May 7, 2020 Issued
Array ( [id] => 16241340 [patent_doc_number] => 20200258574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-13 [patent_title] => APPARATUS FOR DISCHARGING CONTROL GATES AFTER PERFORMING AN ACCESS OPERATION ON A MEMORY CELL [patent_app_type] => utility [patent_app_number] => 16/861435 [patent_app_country] => US [patent_app_date] => 2020-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9421 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16861435 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/861435
Apparatus for discharging control gates after performing an access operation on a memory cell Apr 28, 2020 Issued
Array ( [id] => 17543925 [patent_doc_number] => 11309057 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-19 [patent_title] => Apparatuses and methods for post-package repair protection [patent_app_type] => utility [patent_app_number] => 16/861090 [patent_app_country] => US [patent_app_date] => 2020-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 9867 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16861090 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/861090
Apparatuses and methods for post-package repair protection Apr 27, 2020 Issued
Array ( [id] => 17077745 [patent_doc_number] => 11114157 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-07 [patent_title] => Low resistance monosilicide electrode for phase change memory and methods of making the same [patent_app_type] => utility [patent_app_number] => 16/857053 [patent_app_country] => US [patent_app_date] => 2020-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 26 [patent_no_of_words] => 11923 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16857053 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/857053
Low resistance monosilicide electrode for phase change memory and methods of making the same Apr 22, 2020 Issued
Array ( [id] => 17847732 [patent_doc_number] => 11437116 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-06 [patent_title] => System and method for counting fail bit and reading out the same [patent_app_type] => utility [patent_app_number] => 16/852239 [patent_app_country] => US [patent_app_date] => 2020-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7345 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16852239 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/852239
System and method for counting fail bit and reading out the same Apr 16, 2020 Issued
Array ( [id] => 17158764 [patent_doc_number] => 20210319815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-14 [patent_title] => MEMORY AND CALIBRATION AND OPERATION METHODS THEREOF FOR READING DATA IN MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 16/847629 [patent_app_country] => US [patent_app_date] => 2020-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11385 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16847629 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/847629
Memory and calibration and operation methods thereof for reading data in memory cells Apr 12, 2020 Issued
Array ( [id] => 17130035 [patent_doc_number] => 20210304804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => MEMORY ARRAY WITH MULTIPLEXED SELECT LINES [patent_app_type] => utility [patent_app_number] => 16/831116 [patent_app_country] => US [patent_app_date] => 2020-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14630 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16831116 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/831116
Memory array with multiplexed select lines and two transistor memory cells Mar 25, 2020 Issued
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