Search

Gary Jackson

Supervisory Patent Examiner (ID: 10507, Phone: (571)272-4697 , Office: P/3769 )

Most Active Art Unit
3731
Art Unit(s)
3731, 3734, 4158, 3769, 3304, 3792, 3308, 3309, 3727, 2899, 3407
Total Applications
2094
Issued Applications
1632
Pending Applications
166
Abandoned Applications
295

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10410032 [patent_doc_number] => 20150295042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-15 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/443199 [patent_app_country] => US [patent_app_date] => 2012-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4628 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14443199 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/443199
Semiconductor device in which an insulated-gate bipolar transistor ( IGBT) region and a diode region are formed on one semiconductor substrate Dec 19, 2012 Issued
Array ( [id] => 8882452 [patent_doc_number] => 20130155636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-20 [patent_title] => 'DUMMY THROUGH-SILICON VIA CAPACITOR' [patent_app_type] => utility [patent_app_number] => 13/713667 [patent_app_country] => US [patent_app_date] => 2012-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2758 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13713667 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/713667
DUMMY THROUGH-SILICON VIA CAPACITOR Dec 12, 2012 Abandoned
Array ( [id] => 10433373 [patent_doc_number] => 20150318385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-05 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/443509 [patent_app_country] => US [patent_app_date] => 2012-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4856 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14443509 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/443509
SEMICONDUCTOR DEVICE Dec 4, 2012 Abandoned
Array ( [id] => 9303770 [patent_doc_number] => 20140042444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-13 [patent_title] => 'PIXEL STRUCTURE AND FABRICATING METHOD OF PIXEL STRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/689775 [patent_app_country] => US [patent_app_date] => 2012-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5862 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13689775 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/689775
PIXEL STRUCTURE AND FABRICATING METHOD OF PIXEL STRUCTURE Nov 29, 2012 Abandoned
Array ( [id] => 13950793 [patent_doc_number] => 10211175 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-19 [patent_title] => Stress-resilient chip structure and dicing process [patent_app_type] => utility [patent_app_number] => 13/689805 [patent_app_country] => US [patent_app_date] => 2012-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 5550 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 399 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13689805 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/689805
Stress-resilient chip structure and dicing process Nov 29, 2012 Issued
Array ( [id] => 10080075 [patent_doc_number] => 09117931 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-25 [patent_title] => 'Semiconductor device with a resonator using acoustic standing wave excited in semiconductor crystal' [patent_app_type] => utility [patent_app_number] => 13/685859 [patent_app_country] => US [patent_app_date] => 2012-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6580 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13685859 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/685859
Semiconductor device with a resonator using acoustic standing wave excited in semiconductor crystal Nov 26, 2012 Issued
Array ( [id] => 13043045 [patent_doc_number] => 10043662 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-07 [patent_title] => Method of forming semiconductor substrate [patent_app_type] => utility [patent_app_number] => 13/681119 [patent_app_country] => US [patent_app_date] => 2012-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 7920 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13681119 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/681119
Method of forming semiconductor substrate Nov 18, 2012 Issued
Array ( [id] => 9363214 [patent_doc_number] => 20140073087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-13 [patent_title] => 'METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/680728 [patent_app_country] => US [patent_app_date] => 2012-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2578 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13680728 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/680728
METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE Nov 18, 2012 Abandoned
Array ( [id] => 9491185 [patent_doc_number] => 20140141591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-22 [patent_title] => 'Method to Improve Charge Trap Flash Memory Core Cell Performance and Reliability' [patent_app_type] => utility [patent_app_number] => 13/680726 [patent_app_country] => US [patent_app_date] => 2012-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4732 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13680726 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/680726
Method to improve charge trap flash memory core cell performance and reliability Nov 18, 2012 Issued
Array ( [id] => 9269282 [patent_doc_number] => 20140024199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-23 [patent_title] => 'SEMICONDUCTOR WAFER DICING METHOD' [patent_app_type] => utility [patent_app_number] => 13/681401 [patent_app_country] => US [patent_app_date] => 2012-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3301 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13681401 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/681401
SEMICONDUCTOR WAFER DICING METHOD Nov 18, 2012 Abandoned
Array ( [id] => 9474243 [patent_doc_number] => 20140131707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-15 [patent_title] => 'METHOD AND DEVICE FOR DETECTING TERMINATION OF ETCHING' [patent_app_type] => utility [patent_app_number] => 14/110128 [patent_app_country] => US [patent_app_date] => 2012-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4819 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14110128 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/110128
METHOD AND DEVICE FOR DETECTING TERMINATION OF ETCHING Nov 11, 2012 Abandoned
Array ( [id] => 9031628 [patent_doc_number] => 20130234266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-12 [patent_title] => 'MAGNETIC TUNNEL JUNCTION WITH AN IMPROVED TUNNEL BARRIER' [patent_app_type] => utility [patent_app_number] => 13/604035 [patent_app_country] => US [patent_app_date] => 2012-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2703 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13604035 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/604035
Magnetic tunnel junction with an improved tunnel barrier Sep 4, 2012 Issued
Array ( [id] => 9316603 [patent_doc_number] => 20140048941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-20 [patent_title] => 'Contact Pads with Sidewall Spacers and Method of Making Contact Pads with Sidewall Spacers' [patent_app_type] => utility [patent_app_number] => 13/587809 [patent_app_country] => US [patent_app_date] => 2012-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3653 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13587809 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/587809
Contact pads with sidewall spacers and method of making contact pads with sidewall spacers Aug 15, 2012 Issued
Array ( [id] => 8973837 [patent_doc_number] => 20130207267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-15 [patent_title] => 'INTERCONNECTION STRUCTURES IN A SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/586985 [patent_app_country] => US [patent_app_date] => 2012-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5508 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13586985 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/586985
INTERCONNECTION STRUCTURES IN A SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING THE SAME Aug 15, 2012 Abandoned
Array ( [id] => 9316565 [patent_doc_number] => 20140048903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-20 [patent_title] => 'METHOD AND SYSTEM FOR EDGE TERMINATION IN GAN MATERIALS BY SELECTIVE AREA IMPLANTATION DOPING' [patent_app_type] => utility [patent_app_number] => 13/586330 [patent_app_country] => US [patent_app_date] => 2012-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6145 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13586330 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/586330
METHOD AND SYSTEM FOR EDGE TERMINATION IN GAN MATERIALS BY SELECTIVE AREA IMPLANTATION DOPING Aug 14, 2012 Abandoned
Array ( [id] => 8668983 [patent_doc_number] => 20130043521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-21 [patent_title] => '3-DIMENSIONAL NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/585336 [patent_app_country] => US [patent_app_date] => 2012-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5860 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13585336 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/585336
3-DIMENSIONAL NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME Aug 13, 2012 Abandoned
Array ( [id] => 9132120 [patent_doc_number] => 20130292832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-07 [patent_title] => 'SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/584965 [patent_app_country] => US [patent_app_date] => 2012-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3466 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13584965 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/584965
SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF Aug 13, 2012 Abandoned
Array ( [id] => 9009295 [patent_doc_number] => 08524592 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-09-03 [patent_title] => 'Methods of forming semiconductor devices with self-aligned contacts and low-k spacers and the resulting devices' [patent_app_type] => utility [patent_app_number] => 13/584055 [patent_app_country] => US [patent_app_date] => 2012-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 6536 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13584055 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/584055
Methods of forming semiconductor devices with self-aligned contacts and low-k spacers and the resulting devices Aug 12, 2012 Issued
Array ( [id] => 8499557 [patent_doc_number] => 20120298965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-29 [patent_title] => 'MULTIGATE STRUCTURE FORMED WITH ELECTROLESS METAL DEPOSITION' [patent_app_type] => utility [patent_app_number] => 13/568839 [patent_app_country] => US [patent_app_date] => 2012-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2709 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13568839 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/568839
Multigate structure formed with electroless metal deposition Aug 6, 2012 Issued
Array ( [id] => 8499693 [patent_doc_number] => 20120299101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-29 [patent_title] => 'THIN BODY SILICON-ON-INSULATOR TRANSISTOR WITH BORDERLESS SELF-ALIGNED CONTACTS' [patent_app_type] => utility [patent_app_number] => 13/568655 [patent_app_country] => US [patent_app_date] => 2012-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3118 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13568655 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/568655
THIN BODY SILICON-ON-INSULATOR TRANSISTOR WITH BORDERLESS SELF-ALIGNED CONTACTS Aug 6, 2012 Abandoned
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