Search

Gary W. Cygiel

Examiner (ID: 19348, Phone: (571)270-1170 , Office: P/2137 )

Most Active Art Unit
2137
Art Unit(s)
2187, 2137, 2188
Total Applications
640
Issued Applications
458
Pending Applications
38
Abandoned Applications
153

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13875993 [patent_doc_number] => 20190034337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-31 [patent_title] => MULTI-LEVEL SYSTEM MEMORY CONFIGURATIONS TO OPERATE HIGHER PRIORITY USERS OUT OF A FASTER MEMORY LEVEL [patent_app_type] => utility [patent_app_number] => 15/857463 [patent_app_country] => US [patent_app_date] => 2017-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5706 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15857463 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/857463
MULTI-LEVEL SYSTEM MEMORY CONFIGURATIONS TO OPERATE HIGHER PRIORITY USERS OUT OF A FASTER MEMORY LEVEL Dec 27, 2017 Abandoned
Array ( [id] => 13905897 [patent_doc_number] => 20190042153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => MASS STORAGE DEVICE CAPABLE OF FINE GRAINED READ AND/OR WRITE OPERATIONS [patent_app_type] => utility [patent_app_number] => 15/857406 [patent_app_country] => US [patent_app_date] => 2017-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4738 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15857406 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/857406
MASS STORAGE DEVICE CAPABLE OF FINE GRAINED READ AND/OR WRITE OPERATIONS Dec 27, 2017 Abandoned
Array ( [id] => 12868969 [patent_doc_number] => 20180181498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => METHOD AND SYSTEM FOR CO-PRIVILEGED SECURITY DOMAINS [patent_app_type] => utility [patent_app_number] => 15/857118 [patent_app_country] => US [patent_app_date] => 2017-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5821 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15857118 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/857118
Method and system for co-privileged security domains Dec 27, 2017 Issued
Array ( [id] => 17106346 [patent_doc_number] => 11126563 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-21 [patent_title] => System and method for tracking changes in system memory [patent_app_type] => utility [patent_app_number] => 15/857076 [patent_app_country] => US [patent_app_date] => 2017-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7992 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15857076 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/857076
System and method for tracking changes in system memory Dec 27, 2017 Issued
Array ( [id] => 13906567 [patent_doc_number] => 20190042488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => SHARED MEMORY CONTROLLER IN A DATA CENTER [patent_app_type] => utility [patent_app_number] => 15/857337 [patent_app_country] => US [patent_app_date] => 2017-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13050 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15857337 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/857337
SHARED MEMORY CONTROLLER IN A DATA CENTER Dec 27, 2017 Abandoned
Array ( [id] => 13905837 [patent_doc_number] => 20190042123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => BI-DIRECTIONAL NEGOTIATION FOR DYNAMIC DATA CHUNKING [patent_app_type] => utility [patent_app_number] => 15/857158 [patent_app_country] => US [patent_app_date] => 2017-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13190 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15857158 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/857158
Bi-directional negotiation for dynamic data chunking Dec 27, 2017 Issued
Array ( [id] => 16637280 [patent_doc_number] => 10915791 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-09 [patent_title] => Storing and retrieving training data for models in a data center [patent_app_type] => utility [patent_app_number] => 15/855891 [patent_app_country] => US [patent_app_date] => 2017-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 11267 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15855891 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/855891
Storing and retrieving training data for models in a data center Dec 26, 2017 Issued
Array ( [id] => 13974325 [patent_doc_number] => 10216519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-26 [patent_title] => Multicopy atomic store operation in a data processing system [patent_app_type] => utility [patent_app_number] => 15/825387 [patent_app_country] => US [patent_app_date] => 2017-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 13686 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15825387 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/825387
Multicopy atomic store operation in a data processing system Nov 28, 2017 Issued
Array ( [id] => 13569175 [patent_doc_number] => 20180336135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-22 [patent_title] => OWNERSHIP TRACKING UPDATES ACROSS MULTIPLE SIMULTANEOUS OPERATIONS [patent_app_type] => utility [patent_app_number] => 15/817717 [patent_app_country] => US [patent_app_date] => 2017-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9697 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15817717 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/817717
Ownership tracking updates across multiple simultaneous operations Nov 19, 2017 Issued
Array ( [id] => 14047531 [patent_doc_number] => 20190079872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-14 [patent_title] => CONTROLLING A RATE OF PREFETCHING BASED ON BUS BANDWIDTH [patent_app_type] => utility [patent_app_number] => 15/812570 [patent_app_country] => US [patent_app_date] => 2017-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7232 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15812570 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/812570
Controlling a rate of prefetching based on bus bandwidth Nov 13, 2017 Issued
Array ( [id] => 12612120 [patent_doc_number] => 20180095870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => NVS THRESHOLDING FOR EFFICIENT DATA MANAGEMENT [patent_app_type] => utility [patent_app_number] => 15/809073 [patent_app_country] => US [patent_app_date] => 2017-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4637 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15809073 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/809073
NVS thresholding for efficient data management Nov 9, 2017 Issued
Array ( [id] => 12532236 [patent_doc_number] => 10007600 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-26 [patent_title] => NVS thresholding for efficient data management [patent_app_type] => utility [patent_app_number] => 15/809084 [patent_app_country] => US [patent_app_date] => 2017-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4637 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15809084 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/809084
NVS thresholding for efficient data management Nov 9, 2017 Issued
Array ( [id] => 12262363 [patent_doc_number] => 20180081559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'PROVISIONING OF EXTERNAL MEMORY' [patent_app_type] => utility [patent_app_number] => 15/800891 [patent_app_country] => US [patent_app_date] => 2017-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 37123 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15800891 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/800891
Management of external memory Oct 31, 2017 Issued
Array ( [id] => 13451267 [patent_doc_number] => 20180277176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => MEMORY SYSTEM AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/795453 [patent_app_country] => US [patent_app_date] => 2017-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11557 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15795453 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/795453
MEMORY SYSTEM AND OPERATING METHOD THEREOF Oct 26, 2017 Abandoned
Array ( [id] => 15982403 [patent_doc_number] => 10671529 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Address scheduling methods for non-volatile memory devices with three-dimensional memory cell arrays [patent_app_type] => utility [patent_app_number] => 15/790583 [patent_app_country] => US [patent_app_date] => 2017-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9822 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15790583 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/790583
Address scheduling methods for non-volatile memory devices with three-dimensional memory cell arrays Oct 22, 2017 Issued
Array ( [id] => 12140176 [patent_doc_number] => 20180018259 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-18 [patent_title] => 'APPARATUS AND METHOD FOR LOW POWER LOW LATENCY HIGH CAPACITY STORAGE CLASS MEMORY' [patent_app_type] => utility [patent_app_number] => 15/716467 [patent_app_country] => US [patent_app_date] => 2017-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4988 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15716467 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/716467
Apparatus and method for low power low latency high capacity storage class memory Sep 25, 2017 Issued
Array ( [id] => 12121085 [patent_doc_number] => 20180004672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'CACHE UNIT AND PROCESSOR' [patent_app_type] => utility [patent_app_number] => 15/707871 [patent_app_country] => US [patent_app_date] => 2017-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4506 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15707871 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/707871
Cache memory for particular data Sep 17, 2017 Issued
Array ( [id] => 15919639 [patent_doc_number] => 10657059 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-19 [patent_title] => Controlling a rate of prefetching based on bus bandwidth [patent_app_type] => utility [patent_app_number] => 15/701508 [patent_app_country] => US [patent_app_date] => 2017-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 7460 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15701508 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/701508
Controlling a rate of prefetching based on bus bandwidth Sep 11, 2017 Issued
Array ( [id] => 16355491 [patent_doc_number] => 10796003 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-06 [patent_title] => Divided integrity verification using memory segment protection [patent_app_type] => utility [patent_app_number] => 15/701082 [patent_app_country] => US [patent_app_date] => 2017-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 47 [patent_no_of_words] => 24670 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15701082 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/701082
Divided integrity verification using memory segment protection Sep 10, 2017 Issued
Array ( [id] => 14022563 [patent_doc_number] => 20190073275 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-07 [patent_title] => DATA ARCHIVE TIER OF A TIERED STORAGE SYSTEM [patent_app_type] => utility [patent_app_number] => 15/697732 [patent_app_country] => US [patent_app_date] => 2017-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11351 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15697732 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/697732
Data archive tier of a tiered storage system Sep 6, 2017 Issued
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