Search

Gary W. Cygiel

Examiner (ID: 18831, Phone: (571)270-1170 , Office: P/2137 )

Most Active Art Unit
2137
Art Unit(s)
2188, 2187, 2137
Total Applications
621
Issued Applications
445
Pending Applications
36
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17794152 [patent_doc_number] => 20220253244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => METHOD OF OPERATING HOST AND MEMORY SYSTEM CONNECTED THERETO [patent_app_type] => utility [patent_app_number] => 17/374492 [patent_app_country] => US [patent_app_date] => 2021-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14588 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17374492 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/374492
Method of operating host and memory system connected thereto Jul 12, 2021 Issued
Array ( [id] => 17962007 [patent_doc_number] => 20220342588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => Address Hashing in a Multiple Memory Controller System [patent_app_type] => utility [patent_app_number] => 17/353349 [patent_app_country] => US [patent_app_date] => 2021-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16231 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17353349 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/353349
Address hashing in a multiple memory controller system Jun 20, 2021 Issued
Array ( [id] => 18066937 [patent_doc_number] => 20220398025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-15 [patent_title] => HIGHLY CONCURRENT DATA STORE ALLOCATION [patent_app_type] => utility [patent_app_number] => 17/347491 [patent_app_country] => US [patent_app_date] => 2021-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8062 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17347491 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/347491
Highly concurrent data store allocation Jun 13, 2021 Issued
Array ( [id] => 18006940 [patent_doc_number] => 20220365706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => DATA ACCESSING METHOD, MEMORY CONTROLLING CIRCUIT UNIT, AND MEMORY STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/336347 [patent_app_country] => US [patent_app_date] => 2021-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11778 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17336347 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/336347
Method for adjusting a read voltage level or log likelihood ratio of a memory based on a calculated bit change ratio, memory controlling circuit unit, and memory storage device Jun 1, 2021 Issued
Array ( [id] => 17722084 [patent_doc_number] => 20220214806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => METHOD, ELECTRONIC DEVICE AND COMPUTER PROGRAM PRODUCT FOR STORAGE MANAGEMENT [patent_app_type] => utility [patent_app_number] => 17/316960 [patent_app_country] => US [patent_app_date] => 2021-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4956 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17316960 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/316960
Method, electronic device and computer program product for storage management May 10, 2021 Issued
Array ( [id] => 17786541 [patent_doc_number] => 11409665 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-08-09 [patent_title] => Partial logical-to-physical (L2P) address translation table for multiple namespaces [patent_app_type] => utility [patent_app_number] => 17/315575 [patent_app_country] => US [patent_app_date] => 2021-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 8446 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17315575 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/315575
Partial logical-to-physical (L2P) address translation table for multiple namespaces May 9, 2021 Issued
Array ( [id] => 17301724 [patent_doc_number] => 20210397563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-23 [patent_title] => Data processing method for improving access performance of memory device and data storage device utilizing the same [patent_app_type] => utility [patent_app_number] => 17/246707 [patent_app_country] => US [patent_app_date] => 2021-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8047 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17246707 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/246707
Data processing method for improving access performance of memory device and data storage device utilizing the same May 1, 2021 Issued
Array ( [id] => 17009235 [patent_doc_number] => 20210240396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/235819 [patent_app_country] => US [patent_app_date] => 2021-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5594 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17235819 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/235819
STORAGE DEVICE Apr 19, 2021 Abandoned
Array ( [id] => 18189222 [patent_doc_number] => 11579807 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Efficiently accessing, storing and transmitting data elements [patent_app_type] => utility [patent_app_number] => 17/225938 [patent_app_country] => US [patent_app_date] => 2021-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 24334 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17225938 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/225938
Efficiently accessing, storing and transmitting data elements Apr 7, 2021 Issued
Array ( [id] => 17535298 [patent_doc_number] => 20220113907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/184993 [patent_app_country] => US [patent_app_date] => 2021-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6427 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17184993 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/184993
Memory system Feb 24, 2021 Issued
Array ( [id] => 17475764 [patent_doc_number] => 20220083268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => Storage System and Method for Time-Based Data Retrieval [patent_app_type] => utility [patent_app_number] => 17/176818 [patent_app_country] => US [patent_app_date] => 2021-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6129 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17176818 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/176818
Storage system and method for time-based data retrieval Feb 15, 2021 Issued
Array ( [id] => 18719838 [patent_doc_number] => 11797181 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Hardware accessible external memory [patent_app_type] => utility [patent_app_number] => 17/170280 [patent_app_country] => US [patent_app_date] => 2021-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 35824 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17170280 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/170280
Hardware accessible external memory Feb 7, 2021 Issued
Array ( [id] => 17401510 [patent_doc_number] => 20220043600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => MEMORY CONTROLLER AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/161155 [patent_app_country] => US [patent_app_date] => 2021-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12356 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17161155 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/161155
Memory controller and operating method thereof Jan 27, 2021 Issued
Array ( [id] => 16780242 [patent_doc_number] => 20210117321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => ADDRESS SCHEDULING METHODS FOR NON-VOLATILE MEMORY DEVICES WITH THREE-DIMENSIONAL MEMORY CELL ARRAYS [patent_app_type] => utility [patent_app_number] => 17/137942 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9864 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17137942 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/137942
Address scheduling methods for non-volatile memory devices with three-dimensional memory cell arrays Dec 29, 2020 Issued
Array ( [id] => 16921604 [patent_doc_number] => 20210194696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => SYSTEM AND METHOD FOR HIGH PERFORMANCE SECURE ACCESS TO A TRUSTED PLATFORM MODULE ON A HARDWARE VIRTUALIZATION PLATFORM [patent_app_type] => utility [patent_app_number] => 17/133166 [patent_app_country] => US [patent_app_date] => 2020-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7831 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17133166 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/133166
System and method for high performance secure access to a trusted platform module on a hardware virtualization platform Dec 22, 2020 Issued
Array ( [id] => 16826255 [patent_doc_number] => 20210141548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-13 [patent_title] => PAGING OF EXTERNAL MEMORY [patent_app_type] => utility [patent_app_number] => 17/125542 [patent_app_country] => US [patent_app_date] => 2020-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 46088 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17125542 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/125542
Paging of external memory Dec 16, 2020 Issued
Array ( [id] => 17675077 [patent_doc_number] => 20220188244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => DYNAMIC LOGICAL PAGE SIZES FOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/117907 [patent_app_country] => US [patent_app_date] => 2020-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19512 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17117907 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/117907
Dynamic logical page sizes for memory devices Dec 9, 2020 Issued
Array ( [id] => 17629121 [patent_doc_number] => 20220164136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => GATE SIGNAL CONTROL CIRCUIT FOR DDR MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/953549 [patent_app_country] => US [patent_app_date] => 2020-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7097 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16953549 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/953549
Gate signal control circuit for DDR memory system Nov 19, 2020 Issued
Array ( [id] => 16690662 [patent_doc_number] => 20210073140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => HARDWARE ASSISTED DATA LOOKUP METHODS [patent_app_type] => utility [patent_app_number] => 16/953079 [patent_app_country] => US [patent_app_date] => 2020-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9761 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16953079 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/953079
Logic module for use with encoded instructions Nov 18, 2020 Issued
Array ( [id] => 17581002 [patent_doc_number] => 20220137857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => PULSE AMPLITUDE MODULATION (PAM) FOR MULTI-HOST SUPPORT IN A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 17/088364 [patent_app_country] => US [patent_app_date] => 2020-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8123 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17088364 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/088364
Pulse amplitude modulation (PAM) for multi-host support in a memory sub-system Nov 2, 2020 Issued
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