Search

Gary W. Cygiel

Examiner (ID: 19348, Phone: (571)270-1170 , Office: P/2137 )

Most Active Art Unit
2137
Art Unit(s)
2187, 2137, 2188
Total Applications
640
Issued Applications
458
Pending Applications
38
Abandoned Applications
153

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17475764 [patent_doc_number] => 20220083268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => Storage System and Method for Time-Based Data Retrieval [patent_app_type] => utility [patent_app_number] => 17/176818 [patent_app_country] => US [patent_app_date] => 2021-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6129 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17176818 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/176818
Storage system and method for time-based data retrieval Feb 15, 2021 Issued
Array ( [id] => 18719838 [patent_doc_number] => 11797181 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Hardware accessible external memory [patent_app_type] => utility [patent_app_number] => 17/170280 [patent_app_country] => US [patent_app_date] => 2021-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 35824 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17170280 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/170280
Hardware accessible external memory Feb 7, 2021 Issued
Array ( [id] => 17401510 [patent_doc_number] => 20220043600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => MEMORY CONTROLLER AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/161155 [patent_app_country] => US [patent_app_date] => 2021-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12356 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17161155 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/161155
Memory controller and operating method thereof Jan 27, 2021 Issued
Array ( [id] => 16780242 [patent_doc_number] => 20210117321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => ADDRESS SCHEDULING METHODS FOR NON-VOLATILE MEMORY DEVICES WITH THREE-DIMENSIONAL MEMORY CELL ARRAYS [patent_app_type] => utility [patent_app_number] => 17/137942 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9864 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17137942 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/137942
Address scheduling methods for non-volatile memory devices with three-dimensional memory cell arrays Dec 29, 2020 Issued
Array ( [id] => 16921604 [patent_doc_number] => 20210194696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => SYSTEM AND METHOD FOR HIGH PERFORMANCE SECURE ACCESS TO A TRUSTED PLATFORM MODULE ON A HARDWARE VIRTUALIZATION PLATFORM [patent_app_type] => utility [patent_app_number] => 17/133166 [patent_app_country] => US [patent_app_date] => 2020-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7831 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17133166 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/133166
System and method for high performance secure access to a trusted platform module on a hardware virtualization platform Dec 22, 2020 Issued
Array ( [id] => 16826255 [patent_doc_number] => 20210141548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-13 [patent_title] => PAGING OF EXTERNAL MEMORY [patent_app_type] => utility [patent_app_number] => 17/125542 [patent_app_country] => US [patent_app_date] => 2020-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 46088 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17125542 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/125542
Paging of external memory Dec 16, 2020 Issued
Array ( [id] => 17675077 [patent_doc_number] => 20220188244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => DYNAMIC LOGICAL PAGE SIZES FOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/117907 [patent_app_country] => US [patent_app_date] => 2020-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19512 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17117907 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/117907
Dynamic logical page sizes for memory devices Dec 9, 2020 Issued
Array ( [id] => 17629121 [patent_doc_number] => 20220164136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => GATE SIGNAL CONTROL CIRCUIT FOR DDR MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/953549 [patent_app_country] => US [patent_app_date] => 2020-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7097 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16953549 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/953549
Gate signal control circuit for DDR memory system Nov 19, 2020 Issued
Array ( [id] => 16690662 [patent_doc_number] => 20210073140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => HARDWARE ASSISTED DATA LOOKUP METHODS [patent_app_type] => utility [patent_app_number] => 16/953079 [patent_app_country] => US [patent_app_date] => 2020-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9761 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16953079 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/953079
Logic module for use with encoded instructions Nov 18, 2020 Issued
Array ( [id] => 17581002 [patent_doc_number] => 20220137857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => PULSE AMPLITUDE MODULATION (PAM) FOR MULTI-HOST SUPPORT IN A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 17/088364 [patent_app_country] => US [patent_app_date] => 2020-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8123 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17088364 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/088364
Pulse amplitude modulation (PAM) for multi-host support in a memory sub-system Nov 2, 2020 Issued
Array ( [id] => 17294063 [patent_doc_number] => 20210389902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-16 [patent_title] => MEMORY SYSTEM, MEMORY CONTROLLER, AND OPERATION METHOD OF MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/087404 [patent_app_country] => US [patent_app_date] => 2020-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11185 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17087404 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/087404
Memory system, memory controller, and operation method of memory system Nov 1, 2020 Issued
Array ( [id] => 17581001 [patent_doc_number] => 20220137856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => PROGRAM OPERATION EXECUTION DURING PROGRAM OPERATION SUSPEND [patent_app_type] => utility [patent_app_number] => 16/949452 [patent_app_country] => US [patent_app_date] => 2020-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8721 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16949452 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/949452
PROGRAM OPERATION EXECUTION DURING PROGRAM OPERATION SUSPEND Oct 28, 2020 Abandoned
Array ( [id] => 19259368 [patent_doc_number] => 12019422 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-25 [patent_title] => Control device with attribute setting for industrial machine, attribute setting system for control device for industrial machine, method of setting control device with attributes for industrial machine, and information storage medium for setting a control device with attributes [patent_app_type] => utility [patent_app_number] => 17/082021 [patent_app_country] => US [patent_app_date] => 2020-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9504 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17082021 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/082021
Control device with attribute setting for industrial machine, attribute setting system for control device for industrial machine, method of setting control device with attributes for industrial machine, and information storage medium for setting a control device with attributes Oct 27, 2020 Issued
Array ( [id] => 19228625 [patent_doc_number] => 12008262 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Read voltage control method, memory storage device and memory control circuit unit [patent_app_type] => utility [patent_app_number] => 17/080854 [patent_app_country] => US [patent_app_date] => 2020-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 9028 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17080854 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/080854
Read voltage control method, memory storage device and memory control circuit unit Oct 26, 2020 Issued
Array ( [id] => 18506205 [patent_doc_number] => 11704019 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-18 [patent_title] => Memory system, host device and information processing system for error correction processing [patent_app_type] => utility [patent_app_number] => 17/078547 [patent_app_country] => US [patent_app_date] => 2020-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 24 [patent_no_of_words] => 10544 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17078547 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/078547
Memory system, host device and information processing system for error correction processing Oct 22, 2020 Issued
Array ( [id] => 17565037 [patent_doc_number] => 20220129186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => CONTROLLING ACCESS REQUESTS OF REQUEST NODES [patent_app_type] => utility [patent_app_number] => 17/078304 [patent_app_country] => US [patent_app_date] => 2020-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6349 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17078304 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/078304
Controlling access requests of request nodes Oct 22, 2020 Issued
Array ( [id] => 17535294 [patent_doc_number] => 20220113903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => SINGLE MEMORY BANK STORAGE FOR SERVICING MEMORY ACCESS COMMANDS [patent_app_type] => utility [patent_app_number] => 17/069740 [patent_app_country] => US [patent_app_date] => 2020-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8141 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17069740 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/069740
SINGLE MEMORY BANK STORAGE FOR SERVICING MEMORY ACCESS COMMANDS Oct 12, 2020 Abandoned
Array ( [id] => 17957750 [patent_doc_number] => 11483879 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-25 [patent_title] => Forward error correction systems and methods [patent_app_type] => utility [patent_app_number] => 17/063447 [patent_app_country] => US [patent_app_date] => 2020-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 13520 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17063447 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/063447
Forward error correction systems and methods Oct 4, 2020 Issued
Array ( [id] => 17977261 [patent_doc_number] => 11494120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-08 [patent_title] => Adaptive memory transaction scheduling [patent_app_type] => utility [patent_app_number] => 17/061889 [patent_app_country] => US [patent_app_date] => 2020-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12705 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17061889 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/061889
Adaptive memory transaction scheduling Oct 1, 2020 Issued
Array ( [id] => 16729598 [patent_doc_number] => 20210096745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => MEMORY MANAGEMENT DEVICE CAPABLE OF MANAGING MEMORY ADDRESS TRANSLATION TABLE USING HETEROGENEOUS MEMORIES AND METHOD OF MANAGING MEMORY ADDRESS THEREBY [patent_app_type] => utility [patent_app_number] => 17/026963 [patent_app_country] => US [patent_app_date] => 2020-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5668 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17026963 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/026963
Memory management device capable of managing memory address translation table using heterogeneous memories and method of managing memory address thereby Sep 20, 2020 Issued
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