Search

Gary Wayne Estremsky

Examiner (ID: 16289, Phone: (571)272-7055 , Office: P/3677 )

Most Active Art Unit
3677
Art Unit(s)
3508, 3677, 3627, 3676, 3675, 3673, 3642
Total Applications
2613
Issued Applications
1972
Pending Applications
116
Abandoned Applications
532

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8949084 [patent_doc_number] => 20130194864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-01 [patent_title] => 'IMPLEMENTING ENHANCED DATA WRITE FOR MULTI-LEVEL CELL (MLC) MEMORY USING THRESHOLD VOLTAGE-DRIFT OR RESISTANCE DRIFT TOLERANT MOVING BASELINE MEMORY DATA ENCODING' [patent_app_type] => utility [patent_app_number] => 13/361905 [patent_app_country] => US [patent_app_date] => 2012-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 7562 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13361905 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/361905
Implementing enhanced data write for multi-level cell (MLC) memory using threshold voltage-drift or resistance drift tolerant moving baseline memory data encoding Jan 29, 2012 Issued
Array ( [id] => 9531356 [patent_doc_number] => 08755237 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-17 [patent_title] => 'SRAM power reduction through selective programming' [patent_app_type] => utility [patent_app_number] => 13/359827 [patent_app_country] => US [patent_app_date] => 2012-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 3788 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13359827 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/359827
SRAM power reduction through selective programming Jan 26, 2012 Issued
Array ( [id] => 8556691 [patent_doc_number] => 08331169 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-12-11 [patent_title] => 'Determining threshold voltage distribution in flash memory' [patent_app_type] => utility [patent_app_number] => 13/323787 [patent_app_country] => US [patent_app_date] => 2011-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6271 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13323787 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/323787
Determining threshold voltage distribution in flash memory Dec 11, 2011 Issued
Array ( [id] => 8539387 [patent_doc_number] => 08315110 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-20 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 13/315967 [patent_app_country] => US [patent_app_date] => 2011-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5413 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13315967 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/315967
Nonvolatile semiconductor memory device Dec 8, 2011 Issued
Array ( [id] => 8539387 [patent_doc_number] => 08315110 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-20 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 13/315967 [patent_app_country] => US [patent_app_date] => 2011-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5413 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13315967 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/315967
Nonvolatile semiconductor memory device Dec 8, 2011 Issued
Array ( [id] => 8539387 [patent_doc_number] => 08315110 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-20 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 13/315967 [patent_app_country] => US [patent_app_date] => 2011-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5413 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13315967 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/315967
Nonvolatile semiconductor memory device Dec 8, 2011 Issued
Array ( [id] => 8539387 [patent_doc_number] => 08315110 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-20 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 13/315967 [patent_app_country] => US [patent_app_date] => 2011-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5413 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13315967 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/315967
Nonvolatile semiconductor memory device Dec 8, 2011 Issued
Array ( [id] => 8935585 [patent_doc_number] => 08495302 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-23 [patent_title] => 'Selecting a target number of pages for allocation to a partition' [patent_app_type] => utility [patent_app_number] => 13/308121 [patent_app_country] => US [patent_app_date] => 2011-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 11699 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13308121 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/308121
Selecting a target number of pages for allocation to a partition Nov 29, 2011 Issued
Array ( [id] => 8039867 [patent_doc_number] => 20120069671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-22 [patent_title] => 'MEMORY AND OPERATION METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 13/306678 [patent_app_country] => US [patent_app_date] => 2011-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5088 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20120069671.pdf [firstpage_image] =>[orig_patent_app_number] => 13306678 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/306678
Memory and operation method therefor Nov 28, 2011 Issued
Array ( [id] => 8983527 [patent_doc_number] => 08514651 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-20 [patent_title] => 'Sharing access to a memory among clients' [patent_app_type] => utility [patent_app_number] => 13/302837 [patent_app_country] => US [patent_app_date] => 2011-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 10516 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13302837 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/302837
Sharing access to a memory among clients Nov 21, 2011 Issued
Array ( [id] => 8182542 [patent_doc_number] => 20120113710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-10 [patent_title] => 'NON-VOLATILE MEMORY ARRAY AND EVICE USING ERASE MARKERS' [patent_app_type] => utility [patent_app_number] => 13/289277 [patent_app_country] => US [patent_app_date] => 2011-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4734 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20120113710.pdf [firstpage_image] =>[orig_patent_app_number] => 13289277 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/289277
Non-volatile memory array and device using erase markers Nov 3, 2011 Issued
Array ( [id] => 8714719 [patent_doc_number] => 08400864 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-03-19 [patent_title] => 'Mechanism for peak power management in a memory' [patent_app_type] => utility [patent_app_number] => 13/286365 [patent_app_country] => US [patent_app_date] => 2011-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3696 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13286365 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/286365
Mechanism for peak power management in a memory Oct 31, 2011 Issued
Array ( [id] => 10846112 [patent_doc_number] => 08873302 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-28 [patent_title] => 'Common doped region with separate gate control for a logic compatible non-volatile memory cell' [patent_app_type] => utility [patent_app_number] => 13/284795 [patent_app_country] => US [patent_app_date] => 2011-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 14873 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13284795 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/284795
Common doped region with separate gate control for a logic compatible non-volatile memory cell Oct 27, 2011 Issued
Array ( [id] => 9609886 [patent_doc_number] => 08787066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-22 [patent_title] => 'Method for forming resistive switching memory elements with improved switching behavior' [patent_app_type] => utility [patent_app_number] => 13/281777 [patent_app_country] => US [patent_app_date] => 2011-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3375 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13281777 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/281777
Method for forming resistive switching memory elements with improved switching behavior Oct 25, 2011 Issued
Array ( [id] => 8579271 [patent_doc_number] => 08345491 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-01 [patent_title] => 'Memory cell write' [patent_app_type] => utility [patent_app_number] => 13/282331 [patent_app_country] => US [patent_app_date] => 2011-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5928 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13282331 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/282331
Memory cell write Oct 25, 2011 Issued
Array ( [id] => 8157055 [patent_doc_number] => 20120099360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-26 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/276351 [patent_app_country] => US [patent_app_date] => 2011-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12517 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20120099360.pdf [firstpage_image] =>[orig_patent_app_number] => 13276351 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/276351
Semiconductor memory device and driving method thereof Oct 18, 2011 Issued
Array ( [id] => 8136801 [patent_doc_number] => 20120092946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-19 [patent_title] => 'MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING DISCHARGE LINES AND METHODS OF FORMING' [patent_app_type] => utility [patent_app_number] => 13/251611 [patent_app_country] => US [patent_app_date] => 2011-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5551 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20120092946.pdf [firstpage_image] =>[orig_patent_app_number] => 13251611 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/251611
Memory devices and memory systems including discharge lines Oct 2, 2011 Issued
Array ( [id] => 7764894 [patent_doc_number] => 20120033523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-09 [patent_title] => 'INPUT CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS AND CONTROLLING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/249691 [patent_app_country] => US [patent_app_date] => 2011-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5700 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20120033523.pdf [firstpage_image] =>[orig_patent_app_number] => 13249691 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/249691
Input circuit of semiconductor memory apparatus and controlling method thereof Sep 29, 2011 Issued
Array ( [id] => 8052465 [patent_doc_number] => 20120075944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-29 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 13/200649 [patent_app_country] => US [patent_app_date] => 2011-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 32137 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20120075944.pdf [firstpage_image] =>[orig_patent_app_number] => 13200649 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/200649
Semiconductor device and manufacturing method thereof Sep 27, 2011 Issued
Array ( [id] => 7730121 [patent_doc_number] => 20120014166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-19 [patent_title] => 'RESISTIVE MEMORY' [patent_app_type] => utility [patent_app_number] => 13/242790 [patent_app_country] => US [patent_app_date] => 2011-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 15767 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20120014166.pdf [firstpage_image] =>[orig_patent_app_number] => 13242790 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/242790
Resistive memory Sep 22, 2011 Issued
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