Search

Gautam Patel

Examiner (ID: 10797)

Most Active Art Unit
2627
Art Unit(s)
2783, 2784, 2656, 2183, 2651, 2315, 2653, 2627, 2655
Total Applications
557
Issued Applications
452
Pending Applications
14
Abandoned Applications
91

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4178033 [patent_doc_number] => 06108774 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Branch prediction with added selector bits to increase branch prediction capacity and flexibility with minimal added bits' [patent_app_type] => 1 [patent_app_number] => 8/994869 [patent_app_country] => US [patent_app_date] => 1997-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 16537 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108774.pdf [firstpage_image] =>[orig_patent_app_number] => 994869 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/994869
Branch prediction with added selector bits to increase branch prediction capacity and flexibility with minimal added bits Dec 18, 1997 Issued
Array ( [id] => 4402505 [patent_doc_number] => 06279103 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Method and device for providing an instruction trace from an on-chip CPU using control signals from the CPU' [patent_app_type] => 1 [patent_app_number] => 8/994358 [patent_app_country] => US [patent_app_date] => 1997-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 15133 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/279/06279103.pdf [firstpage_image] =>[orig_patent_app_number] => 994358 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/994358
Method and device for providing an instruction trace from an on-chip CPU using control signals from the CPU Dec 18, 1997 Issued
Array ( [id] => 1460064 [patent_doc_number] => 06463522 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Memory system for ordering load and store instructions in a processor that performs multithread execution' [patent_app_type] => B1 [patent_app_number] => 08/991734 [patent_app_country] => US [patent_app_date] => 1997-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 38 [patent_no_of_words] => 16666 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/463/06463522.pdf [firstpage_image] =>[orig_patent_app_number] => 08991734 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/991734
Memory system for ordering load and store instructions in a processor that performs multithread execution Dec 15, 1997 Issued
Array ( [id] => 4423832 [patent_doc_number] => 06240509 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Out-of-pipeline trace buffer for holding instructions that may be re-executed following misspeculation' [patent_app_type] => 1 [patent_app_number] => 8/991269 [patent_app_country] => US [patent_app_date] => 1997-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 38 [patent_no_of_words] => 16058 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/240/06240509.pdf [firstpage_image] =>[orig_patent_app_number] => 991269 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/991269
Out-of-pipeline trace buffer for holding instructions that may be re-executed following misspeculation Dec 15, 1997 Issued
Array ( [id] => 4110253 [patent_doc_number] => 06134650 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Apparatus and method for predicting a first scanned instruction as microcode instruction prior to scanning predecode data' [patent_app_type] => 1 [patent_app_number] => 8/989262 [patent_app_country] => US [patent_app_date] => 1997-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 12010 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134650.pdf [firstpage_image] =>[orig_patent_app_number] => 989262 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/989262
Apparatus and method for predicting a first scanned instruction as microcode instruction prior to scanning predecode data Dec 11, 1997 Issued
Array ( [id] => 4123181 [patent_doc_number] => 06101528 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Method and apparatus for discovering server applications by a client application in a network of computer systems' [patent_app_type] => 1 [patent_app_number] => 8/978997 [patent_app_country] => US [patent_app_date] => 1997-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3791 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/101/06101528.pdf [firstpage_image] =>[orig_patent_app_number] => 978997 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/978997
Method and apparatus for discovering server applications by a client application in a network of computer systems Nov 27, 1997 Issued
Array ( [id] => 4148295 [patent_doc_number] => 06016505 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-18 [patent_title] => 'Program product to effect barrier synchronization in a distributed computing environment' [patent_app_type] => 1 [patent_app_number] => 8/976934 [patent_app_country] => US [patent_app_date] => 1997-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 10782 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/016/06016505.pdf [firstpage_image] =>[orig_patent_app_number] => 976934 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/976934
Program product to effect barrier synchronization in a distributed computing environment Nov 23, 1997 Issued
Array ( [id] => 4121275 [patent_doc_number] => 06052712 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'System for barrier synchronization wherein members dynamic voting controls the number of synchronization phases of protocols and progression to each subsequent phase' [patent_app_type] => 1 [patent_app_number] => 8/976680 [patent_app_country] => US [patent_app_date] => 1997-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 10780 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/052/06052712.pdf [firstpage_image] =>[orig_patent_app_number] => 976680 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/976680
System for barrier synchronization wherein members dynamic voting controls the number of synchronization phases of protocols and progression to each subsequent phase Nov 23, 1997 Issued
Array ( [id] => 4239668 [patent_doc_number] => 06012095 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Generic notification framework system and method for enhancing operation of a management station on a network' [patent_app_type] => 1 [patent_app_number] => 8/972830 [patent_app_country] => US [patent_app_date] => 1997-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6400 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/012/06012095.pdf [firstpage_image] =>[orig_patent_app_number] => 972830 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/972830
Generic notification framework system and method for enhancing operation of a management station on a network Nov 17, 1997 Issued
Array ( [id] => 1401297 [patent_doc_number] => 06564310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-13 [patent_title] => 'Data transfer circuit and a recording apparatus and method using a predetermined offset for calculating start' [patent_app_type] => B2 [patent_app_number] => 08/967263 [patent_app_country] => US [patent_app_date] => 1997-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 33 [patent_no_of_words] => 12608 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/564/06564310.pdf [firstpage_image] =>[orig_patent_app_number] => 08967263 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/967263
Data transfer circuit and a recording apparatus and method using a predetermined offset for calculating start Nov 6, 1997 Issued
Array ( [id] => 3996042 [patent_doc_number] => 05918247 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Method for canceling partial line fetch for cache when new data is requested during current fetch and invalidating portion of previously fetched data' [patent_app_type] => 1 [patent_app_number] => 8/958738 [patent_app_country] => US [patent_app_date] => 1997-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3856 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/918/05918247.pdf [firstpage_image] =>[orig_patent_app_number] => 958738 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/958738
Method for canceling partial line fetch for cache when new data is requested during current fetch and invalidating portion of previously fetched data Oct 26, 1997 Issued
Array ( [id] => 4020377 [patent_doc_number] => 05860152 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Method and apparatus for rapid computation of target addresses for relative control transfer instructions' [patent_app_type] => 1 [patent_app_number] => 8/956251 [patent_app_country] => US [patent_app_date] => 1997-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3299 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/860/05860152.pdf [firstpage_image] =>[orig_patent_app_number] => 956251 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/956251
Method and apparatus for rapid computation of target addresses for relative control transfer instructions Oct 21, 1997 Issued
Array ( [id] => 4312366 [patent_doc_number] => 06237077 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Instruction template for efficient processing clustered branch instructions' [patent_app_type] => 1 [patent_app_number] => 8/949277 [patent_app_country] => US [patent_app_date] => 1997-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5300 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/237/06237077.pdf [firstpage_image] =>[orig_patent_app_number] => 949277 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/949277
Instruction template for efficient processing clustered branch instructions Oct 12, 1997 Issued
Array ( [id] => 4057471 [patent_doc_number] => 05875324 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Superscalar microprocessor which delays update of branch prediction information in response to branch misprediction until a subsequent idle clock' [patent_app_type] => 1 [patent_app_number] => 8/947225 [patent_app_country] => US [patent_app_date] => 1997-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 66 [patent_no_of_words] => 101935 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875324.pdf [firstpage_image] =>[orig_patent_app_number] => 947225 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/947225
Superscalar microprocessor which delays update of branch prediction information in response to branch misprediction until a subsequent idle clock Oct 7, 1997 Issued
Array ( [id] => 4333343 [patent_doc_number] => 06317822 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Instruction encoding techniques for microcontroller architecture' [patent_app_type] => 1 [patent_app_number] => 8/943554 [patent_app_country] => US [patent_app_date] => 1997-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4362 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/317/06317822.pdf [firstpage_image] =>[orig_patent_app_number] => 943554 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/943554
Instruction encoding techniques for microcontroller architecture Oct 2, 1997 Issued
Array ( [id] => 4273823 [patent_doc_number] => 06209083 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Processor having selectable exception handling modes' [patent_app_type] => 1 [patent_app_number] => 8/942236 [patent_app_country] => US [patent_app_date] => 1997-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4994 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/209/06209083.pdf [firstpage_image] =>[orig_patent_app_number] => 942236 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/942236
Processor having selectable exception handling modes Sep 30, 1997 Issued
Array ( [id] => 4085384 [patent_doc_number] => 06009508 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'System and method for addressing plurality of data values with a single address in a multi-value store on FIFO basis' [patent_app_type] => 1 [patent_app_number] => 8/938242 [patent_app_country] => US [patent_app_date] => 1997-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11468 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009508.pdf [firstpage_image] =>[orig_patent_app_number] => 938242 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/938242
System and method for addressing plurality of data values with a single address in a multi-value store on FIFO basis Sep 25, 1997 Issued
Array ( [id] => 4036967 [patent_doc_number] => 05968169 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Superscalar microprocessor stack structure for judging validity of predicted subroutine return addresses' [patent_app_type] => 1 [patent_app_number] => 8/937849 [patent_app_country] => US [patent_app_date] => 1997-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 68 [patent_no_of_words] => 73771 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/968/05968169.pdf [firstpage_image] =>[orig_patent_app_number] => 937849 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/937849
Superscalar microprocessor stack structure for judging validity of predicted subroutine return addresses Sep 24, 1997 Issued
Array ( [id] => 3877920 [patent_doc_number] => 05796971 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'Method for generating prefetch instruction with a field specifying type of information and location for it such as an instruction cache or data cache' [patent_app_type] => 1 [patent_app_number] => 8/918707 [patent_app_country] => US [patent_app_date] => 1997-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3636 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/796/05796971.pdf [firstpage_image] =>[orig_patent_app_number] => 918707 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/918707
Method for generating prefetch instruction with a field specifying type of information and location for it such as an instruction cache or data cache Aug 21, 1997 Issued
Array ( [id] => 3872592 [patent_doc_number] => 05768574 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Microprocessor using an instruction field to expand the condition flags and a computer system employing the microprocessor' [patent_app_type] => 1 [patent_app_number] => 8/914698 [patent_app_country] => US [patent_app_date] => 1997-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5306 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/768/05768574.pdf [firstpage_image] =>[orig_patent_app_number] => 914698 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/914698
Microprocessor using an instruction field to expand the condition flags and a computer system employing the microprocessor Aug 18, 1997 Issued
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