Search

Gautam Patel

Examiner (ID: 10797)

Most Active Art Unit
2627
Art Unit(s)
2783, 2784, 2656, 2183, 2651, 2315, 2653, 2627, 2655
Total Applications
557
Issued Applications
452
Pending Applications
14
Abandoned Applications
91

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4292559 [patent_doc_number] => 06247120 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Instruction buffer for issuing instruction sets to an instruction decoder' [patent_app_type] => 1 [patent_app_number] => 8/912048 [patent_app_country] => US [patent_app_date] => 1997-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6048 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/247/06247120.pdf [firstpage_image] =>[orig_patent_app_number] => 912048 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/912048
Instruction buffer for issuing instruction sets to an instruction decoder Aug 14, 1997 Issued
Array ( [id] => 4114741 [patent_doc_number] => 06049867 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Method and system for multi-thread switching only when a cache miss occurs at a second or higher level' [patent_app_type] => 1 [patent_app_number] => 8/906228 [patent_app_country] => US [patent_app_date] => 1997-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5172 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/049/06049867.pdf [firstpage_image] =>[orig_patent_app_number] => 906228 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/906228
Method and system for multi-thread switching only when a cache miss occurs at a second or higher level Aug 3, 1997 Issued
Array ( [id] => 3812458 [patent_doc_number] => 05781802 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'First-in-first-out (FIFO) controller for buffering data between systems which are asynchronous and free of false flags and internal metastability' [patent_app_type] => 1 [patent_app_number] => 8/890127 [patent_app_country] => US [patent_app_date] => 1997-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2050 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/781/05781802.pdf [firstpage_image] =>[orig_patent_app_number] => 890127 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/890127
First-in-first-out (FIFO) controller for buffering data between systems which are asynchronous and free of false flags and internal metastability Jul 8, 1997 Issued
Array ( [id] => 4085428 [patent_doc_number] => 06009511 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Apparatus and method for tagging floating point operands and results for rapid detection of special floating point numbers' [patent_app_type] => 1 [patent_app_number] => 8/873340 [patent_app_country] => US [patent_app_date] => 1997-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12704 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009511.pdf [firstpage_image] =>[orig_patent_app_number] => 873340 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/873340
Apparatus and method for tagging floating point operands and results for rapid detection of special floating point numbers Jun 10, 1997 Issued
Array ( [id] => 3818295 [patent_doc_number] => 05854913 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-29 [patent_title] => 'Microprocessor with an architecture mode control capable of supporting extensions of two distinct instruction-set architectures' [patent_app_type] => 1 [patent_app_number] => 8/872370 [patent_app_country] => US [patent_app_date] => 1997-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11592 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/854/05854913.pdf [firstpage_image] =>[orig_patent_app_number] => 872370 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/872370
Microprocessor with an architecture mode control capable of supporting extensions of two distinct instruction-set architectures Jun 9, 1997 Issued
Array ( [id] => 4148874 [patent_doc_number] => 06016544 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-18 [patent_title] => 'Apparatus and method for tracking changes in address size and for different size retranslate second instruction with an indicator from address size' [patent_app_type] => 1 [patent_app_number] => 8/871040 [patent_app_country] => US [patent_app_date] => 1997-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6996 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/016/06016544.pdf [firstpage_image] =>[orig_patent_app_number] => 871040 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/871040
Apparatus and method for tracking changes in address size and for different size retranslate second instruction with an indicator from address size Jun 8, 1997 Issued
Array ( [id] => 4399500 [patent_doc_number] => 06295601 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'System and method using partial trap barrier instruction to provide trap barrier class-based selective stall of instruction processing pipeline' [patent_app_type] => 1 [patent_app_number] => 8/866101 [patent_app_country] => US [patent_app_date] => 1997-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 10594 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/295/06295601.pdf [firstpage_image] =>[orig_patent_app_number] => 866101 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/866101
System and method using partial trap barrier instruction to provide trap barrier class-based selective stall of instruction processing pipeline May 29, 1997 Issued
Array ( [id] => 4147755 [patent_doc_number] => 06128720 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Distributed processing array with component processors performing customized interpretation of instructions' [patent_app_type] => 1 [patent_app_number] => 8/838803 [patent_app_country] => US [patent_app_date] => 1997-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 13 [patent_no_of_words] => 7459 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128720.pdf [firstpage_image] =>[orig_patent_app_number] => 838803 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/838803
Distributed processing array with component processors performing customized interpretation of instructions Apr 9, 1997 Issued
Array ( [id] => 3898749 [patent_doc_number] => 05748951 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Specialized millicode instructions which reduce cycle time and number of instructions necessary to perform complex operations' [patent_app_type] => 1 [patent_app_number] => 8/829267 [patent_app_country] => US [patent_app_date] => 1997-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5183 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 345 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/748/05748951.pdf [firstpage_image] =>[orig_patent_app_number] => 829267 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/829267
Specialized millicode instructions which reduce cycle time and number of instructions necessary to perform complex operations Mar 30, 1997 Issued
Array ( [id] => 4118461 [patent_doc_number] => 06098167 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Apparatus and method for fast unified interrupt recovery and branch recovery in processors supporting out-of-order execution' [patent_app_type] => 1 [patent_app_number] => 8/829667 [patent_app_country] => US [patent_app_date] => 1997-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 106 [patent_no_of_words] => 17269 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/098/06098167.pdf [firstpage_image] =>[orig_patent_app_number] => 829667 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/829667
Apparatus and method for fast unified interrupt recovery and branch recovery in processors supporting out-of-order execution Mar 30, 1997 Issued
Array ( [id] => 5926558 [patent_doc_number] => 20020116599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-22 [patent_title] => 'DATA PROCESSING APPARATUS' [patent_app_type] => new [patent_app_number] => 08/816500 [patent_app_country] => US [patent_app_date] => 1997-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9227 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20020116599.pdf [firstpage_image] =>[orig_patent_app_number] => 08816500 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/816500
DATA PROCESSING APPARATUS Mar 12, 1997 Abandoned
Array ( [id] => 4422375 [patent_doc_number] => 06233672 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Piping rounding mode bits with floating point instructions to eliminate serialization' [patent_app_type] => 1 [patent_app_number] => 8/812026 [patent_app_country] => US [patent_app_date] => 1997-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13116 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/233/06233672.pdf [firstpage_image] =>[orig_patent_app_number] => 812026 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/812026
Piping rounding mode bits with floating point instructions to eliminate serialization Mar 5, 1997 Issued
Array ( [id] => 4167408 [patent_doc_number] => 06065109 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Arbitration logic using a four-phase signaling protocol for control of a counterflow pipeline processor' [patent_app_type] => 1 [patent_app_number] => 8/795440 [patent_app_country] => US [patent_app_date] => 1997-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 25 [patent_no_of_words] => 7670 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/065/06065109.pdf [firstpage_image] =>[orig_patent_app_number] => 795440 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/795440
Arbitration logic using a four-phase signaling protocol for control of a counterflow pipeline processor Feb 4, 1997 Issued
Array ( [id] => 4167395 [patent_doc_number] => 06065108 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Non-quick instruction accelerator including instruction identifier and data set storage and method of implementing same' [patent_app_type] => 1 [patent_app_number] => 8/788805 [patent_app_country] => US [patent_app_date] => 1997-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 17014 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/065/06065108.pdf [firstpage_image] =>[orig_patent_app_number] => 788805 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/788805
Non-quick instruction accelerator including instruction identifier and data set storage and method of implementing same Jan 22, 1997 Issued
Array ( [id] => 4288145 [patent_doc_number] => 06250821 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Method and apparatus for processing branch instructions in an instruction buffer' [patent_app_type] => 1 [patent_app_number] => 8/787983 [patent_app_country] => US [patent_app_date] => 1997-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6048 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/250/06250821.pdf [firstpage_image] =>[orig_patent_app_number] => 787983 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/787983
Method and apparatus for processing branch instructions in an instruction buffer Jan 22, 1997 Issued
Array ( [id] => 4103980 [patent_doc_number] => 06026485 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Instruction folding for a stack-based machine' [patent_app_type] => 1 [patent_app_number] => 8/786351 [patent_app_country] => US [patent_app_date] => 1997-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 25 [patent_no_of_words] => 43790 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/026/06026485.pdf [firstpage_image] =>[orig_patent_app_number] => 786351 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/786351
Instruction folding for a stack-based machine Jan 22, 1997 Issued
Array ( [id] => 4171658 [patent_doc_number] => 06125439 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Process of executing a method on a stack-based processor' [patent_app_type] => 1 [patent_app_number] => 8/786955 [patent_app_country] => US [patent_app_date] => 1997-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 35041 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/125/06125439.pdf [firstpage_image] =>[orig_patent_app_number] => 786955 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/786955
Process of executing a method on a stack-based processor Jan 22, 1997 Issued
Array ( [id] => 4126975 [patent_doc_number] => 06058471 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Data processing system capable of executing groups of instructions in parallel' [patent_app_type] => 1 [patent_app_number] => 8/759500 [patent_app_country] => US [patent_app_date] => 1996-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 42 [patent_no_of_words] => 17876 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/058/06058471.pdf [firstpage_image] =>[orig_patent_app_number] => 759500 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/759500
Data processing system capable of executing groups of instructions in parallel Dec 3, 1996 Issued
Array ( [id] => 4206904 [patent_doc_number] => 06131158 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Data processing system capable of executing groups of instructions, including at least one arithmetic instruction, in parallel' [patent_app_type] => 1 [patent_app_number] => 8/759499 [patent_app_country] => US [patent_app_date] => 1996-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 44 [patent_no_of_words] => 17883 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/131/06131158.pdf [firstpage_image] =>[orig_patent_app_number] => 759499 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/759499
Data processing system capable of executing groups of instructions, including at least one arithmetic instruction, in parallel Dec 3, 1996 Issued
Array ( [id] => 3969996 [patent_doc_number] => 05991819 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Dual-ported memory controller which maintains cache coherency using a memory line status table' [patent_app_type] => 1 [patent_app_number] => 8/760126 [patent_app_country] => US [patent_app_date] => 1996-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 9708 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/991/05991819.pdf [firstpage_image] =>[orig_patent_app_number] => 760126 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/760126
Dual-ported memory controller which maintains cache coherency using a memory line status table Dec 2, 1996 Issued
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