Search

Gautam Patel

Examiner (ID: 17576)

Most Active Art Unit
2627
Art Unit(s)
2656, 2183, 2784, 2651, 2655, 2627, 2315, 2783, 2653
Total Applications
557
Issued Applications
452
Pending Applications
14
Abandoned Applications
91

Applications

Application numberTitle of the applicationFiling DateStatus
08/473692 METHOD AND SYSTEM FOR ENHANCED MULTITHREAD OPERATION IN A DATA PROCESSING SYSTEM BY REDUCING MEMORY ACCESS LATENCY DELAYS Jun 6, 1995 Abandoned
Array ( [id] => 3744832 [patent_doc_number] => 05694545 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'System for providing control of data transmission by destination node using stream values transmitted from plural source nodes' [patent_app_type] => 1 [patent_app_number] => 8/483831 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6692 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/694/05694545.pdf [firstpage_image] =>[orig_patent_app_number] => 483831 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/483831
System for providing control of data transmission by destination node using stream values transmitted from plural source nodes Jun 6, 1995 Issued
08/484349 COMPUTER INSTRUCTION SET ADDRESSING UTILIZING A REDUCED NUMBER OF ADDRESS BITS Jun 6, 1995 Abandoned
08/479622 INSTRUCTION BUFFER FOR ALIGNING INSTRUCTION SETS USING BOUNDARY DETECTION Jun 6, 1995 Abandoned
08/480105 MICROPROCESSOR WITH AN ARCHITECTURE MODE CONTROL CAPABLE OF SUPPORTING EXTENSIONS OF TWO DISTINCT INSTRUCTION-SET ARCHITECTURES Jun 6, 1995 Abandoned
08/472665 STACK STRUCTURE FOR JUDGING VALIDITY OF PREDICTED SUBROUTINE RETURN ADDRESSES Jun 6, 1995 Abandoned
Array ( [id] => 3603455 [patent_doc_number] => 05586277 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-17 [patent_title] => 'Method for parallel steering of fixed length fields containing a variable length instruction from an instruction buffer to parallel decoders' [patent_app_type] => 1 [patent_app_number] => 8/479867 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 14101 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/586/05586277.pdf [firstpage_image] =>[orig_patent_app_number] => 479867 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/479867
Method for parallel steering of fixed length fields containing a variable length instruction from an instruction buffer to parallel decoders Jun 6, 1995 Issued
Array ( [id] => 3682258 [patent_doc_number] => 05600848 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-04 [patent_title] => 'Counterflow pipeline processor with instructions flowing in a first direction and instruction results flowing in the reverse direction' [patent_app_type] => 1 [patent_app_number] => 8/477533 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 14668 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/600/05600848.pdf [firstpage_image] =>[orig_patent_app_number] => 477533 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/477533
Counterflow pipeline processor with instructions flowing in a first direction and instruction results flowing in the reverse direction Jun 6, 1995 Issued
Array ( [id] => 3700793 [patent_doc_number] => 05696959 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-09 [patent_title] => 'Memory store from a selected one of a register pair conditional upon the state of a selected status bit' [patent_app_type] => 1 [patent_app_number] => 8/478129 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 72 [patent_no_of_words] => 101431 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/696/05696959.pdf [firstpage_image] =>[orig_patent_app_number] => 478129 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/478129
Memory store from a selected one of a register pair conditional upon the state of a selected status bit Jun 6, 1995 Issued
08/481704 MICROPROCESSOR USING AN INSTRUCTION FIELD TO EXPAND THE CONDITION FLAGS AND A COMPUTER SYSTEM EMPLOYING THE MICROPROCESSOR Jun 6, 1995 Abandoned
08/472249 SUPERSCALAR MICROPROCESSOR WHICH DELAYS UPDATE OF BRANCH PREDICTION INFORMATION IN RESPONSE TO BRANCH MISPREDICTION UNTIL A SUBSEQUENT IDLE CLOCK Jun 6, 1995 Abandoned
08/460051 INSTRUCTION BUFFER FOR ALIGNING INSTRUCTION SETS USING BOUNDARY DETECTION Jun 1, 1995 Abandoned
Array ( [id] => 3675743 [patent_doc_number] => 05625808 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-29 [patent_title] => 'Read only store as part of cache store for storing frequently used millicode instructions' [patent_app_type] => 1 [patent_app_number] => 8/455820 [patent_app_country] => US [patent_app_date] => 1995-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4475 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/625/05625808.pdf [firstpage_image] =>[orig_patent_app_number] => 455820 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/455820
Read only store as part of cache store for storing frequently used millicode instructions May 30, 1995 Issued
08/451503 INTEGRATED CIRCUIT WITH MULTIPLE FUNCTIONS SHARING MULTIPLE INTERNAL SIGNAL BUSES ACCORDING TO DISTRIBUTED BUS ACCESS AND CONTROL ARBITRATION May 25, 1995 Abandoned
Array ( [id] => 3673131 [patent_doc_number] => 05649147 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'Circuit for designating instruction pointers for use by a processor decoder' [patent_app_type] => 1 [patent_app_number] => 8/451495 [patent_app_country] => US [patent_app_date] => 1995-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3251 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/649/05649147.pdf [firstpage_image] =>[orig_patent_app_number] => 451495 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/451495
Circuit for designating instruction pointers for use by a processor decoder May 25, 1995 Issued
Array ( [id] => 4076014 [patent_doc_number] => 05896505 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Data transfer system and method for dividing an original data read instruction into individual read demands for each data element' [patent_app_type] => 1 [patent_app_number] => 8/448862 [patent_app_country] => US [patent_app_date] => 1995-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 6163 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/896/05896505.pdf [firstpage_image] =>[orig_patent_app_number] => 448862 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/448862
Data transfer system and method for dividing an original data read instruction into individual read demands for each data element May 23, 1995 Issued
Array ( [id] => 4089221 [patent_doc_number] => 05966529 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'Processor having auxiliary operand register file and complementary arrangements for non-disruptively performing adjunct execution' [patent_app_type] => 1 [patent_app_number] => 8/440993 [patent_app_country] => US [patent_app_date] => 1995-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6501 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/966/05966529.pdf [firstpage_image] =>[orig_patent_app_number] => 440993 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/440993
Processor having auxiliary operand register file and complementary arrangements for non-disruptively performing adjunct execution May 14, 1995 Issued
Array ( [id] => 3675433 [patent_doc_number] => 05625787 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-29 [patent_title] => 'Superscalar instruction pipeline using alignment logic responsive to boundary identification logic for aligning and appending variable length instructions to instructions stored in cache' [patent_app_type] => 1 [patent_app_number] => 8/440034 [patent_app_country] => US [patent_app_date] => 1995-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3554 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 324 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/625/05625787.pdf [firstpage_image] =>[orig_patent_app_number] => 440034 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/440034
Superscalar instruction pipeline using alignment logic responsive to boundary identification logic for aligning and appending variable length instructions to instructions stored in cache May 11, 1995 Issued
Array ( [id] => 3700915 [patent_doc_number] => 05644744 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-01 [patent_title] => 'Superscaler instruction pipeline having boundary identification logic for variable length instructions' [patent_app_type] => 1 [patent_app_number] => 8/440035 [patent_app_country] => US [patent_app_date] => 1995-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3551 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/644/05644744.pdf [firstpage_image] =>[orig_patent_app_number] => 440035 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/440035
Superscaler instruction pipeline having boundary identification logic for variable length instructions May 11, 1995 Issued
Array ( [id] => 4040491 [patent_doc_number] => 05884061 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'Apparatus to perform source operand dependency analysis perform register renaming and provide rapid pipeline recovery for a microprocessor capable of issuing and executing multiple instructions out-of-order in a single processor cycle' [patent_app_type] => 1 [patent_app_number] => 8/797392 [patent_app_country] => US [patent_app_date] => 1995-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4219 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/884/05884061.pdf [firstpage_image] =>[orig_patent_app_number] => 797392 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/797392
Apparatus to perform source operand dependency analysis perform register renaming and provide rapid pipeline recovery for a microprocessor capable of issuing and executing multiple instructions out-of-order in a single processor cycle Apr 30, 1995 Issued
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