| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 14050141
[patent_doc_number] => 20190081178
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-03-14
[patent_title] => THIN FILM TRANSISTOR, ARRAY SUBSTRATE, AND METHOD FOR FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/026307
[patent_app_country] => US
[patent_app_date] => 2018-07-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4032
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16026307
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/026307 | Thin film transistor, array substrate, and method for fabricating the same | Jul 2, 2018 | Issued |
Array
(
[id] => 13485485
[patent_doc_number] => 20180294285
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-10-11
[patent_title] => MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/005615
[patent_app_country] => US
[patent_app_date] => 2018-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 23955
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16005615
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/005615 | Manufacturing method of semiconductor device | Jun 10, 2018 | Issued |
Array
(
[id] => 15984859
[patent_doc_number] => 10672769
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-02
[patent_title] => Method of fabricating a transistor having a drain pad with capping and silicide layers
[patent_app_type] => utility
[patent_app_number] => 15/990271
[patent_app_country] => US
[patent_app_date] => 2018-05-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 15
[patent_no_of_words] => 7963
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15990271
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/990271 | Method of fabricating a transistor having a drain pad with capping and silicide layers | May 24, 2018 | Issued |
Array
(
[id] => 13451905
[patent_doc_number] => 20180277495
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-09-27
[patent_title] => Packages with Interposers and Methods for Forming the Same
[patent_app_type] => utility
[patent_app_number] => 15/989906
[patent_app_country] => US
[patent_app_date] => 2018-05-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2687
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15989906
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/989906 | Packages with interposers and methods for forming the same | May 24, 2018 | Issued |
Array
(
[id] => 15154703
[patent_doc_number] => 20190355829
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-11-21
[patent_title] => INTERFACE-LESS CONTACTS TO SOURCE/DRAIN REGIONS AND GATE ELECTRODE OVER ACTIVE PORTION OF DEVICE
[patent_app_type] => utility
[patent_app_number] => 15/982507
[patent_app_country] => US
[patent_app_date] => 2018-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7167
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15982507
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/982507 | Interface-less contacts to source/drain regions and gate electrode over active portion of device | May 16, 2018 | Issued |
Array
(
[id] => 14707361
[patent_doc_number] => 10381443
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-08-13
[patent_title] => Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device
[patent_app_type] => utility
[patent_app_number] => 15/976442
[patent_app_country] => US
[patent_app_date] => 2018-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 133
[patent_figures_cnt] => 141
[patent_no_of_words] => 35657
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15976442
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/976442 | Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device | May 9, 2018 | Issued |
Array
(
[id] => 14542683
[patent_doc_number] => 20190206963
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-07-04
[patent_title] => DISPLAY PANEL AND METHOD FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 15/945381
[patent_app_country] => US
[patent_app_date] => 2018-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2262
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15945381
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/945381 | DISPLAY PANEL AND METHOD FOR MANUFACTURING THE SAME | Apr 3, 2018 | Abandoned |
Array
(
[id] => 16386678
[patent_doc_number] => 10811523
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-10-20
[patent_title] => Vertical MOSFET having insulated trenches and base region contact
[patent_app_type] => utility
[patent_app_number] => 15/936723
[patent_app_country] => US
[patent_app_date] => 2018-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 16
[patent_no_of_words] => 8077
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 364
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15936723
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/936723 | Vertical MOSFET having insulated trenches and base region contact | Mar 26, 2018 | Issued |
Array
(
[id] => 13613775
[patent_doc_number] => 20180358437
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-12-13
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 15/934896
[patent_app_country] => US
[patent_app_date] => 2018-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9651
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15934896
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/934896 | Semiconductor device with a trench electrode provided inside a trench formed on an upper surface of the semiconductor substrate and method of manufacturing the same | Mar 22, 2018 | Issued |
| 15/918003 | Barrier Inserts for Linear Enhancement-Mode High Electron-Mobility Transistors | Mar 11, 2018 | Abandoned |
Array
(
[id] => 14843405
[patent_doc_number] => 20190280103
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-09-12
[patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 15/916455
[patent_app_country] => US
[patent_app_date] => 2018-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3644
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15916455
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/916455 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME | Mar 8, 2018 | Abandoned |
Array
(
[id] => 17078133
[patent_doc_number] => 11114549
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-09-07
[patent_title] => Semiconductor structure cutting process and structures formed thereby
[patent_app_type] => utility
[patent_app_number] => 15/909800
[patent_app_country] => US
[patent_app_date] => 2018-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 50
[patent_figures_cnt] => 51
[patent_no_of_words] => 10224
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15909800
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/909800 | Semiconductor structure cutting process and structures formed thereby | Feb 28, 2018 | Issued |
Array
(
[id] => 14785167
[patent_doc_number] => 20190267481
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-29
[patent_title] => Field-Effect Transistors (FETs)
[patent_app_type] => utility
[patent_app_number] => 15/905295
[patent_app_country] => US
[patent_app_date] => 2018-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6509
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15905295
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/905295 | Field-Effect Transistors (FETs) | Feb 25, 2018 | Abandoned |
Array
(
[id] => 12849847
[patent_doc_number] => 20180175122
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-21
[patent_title] => ORGANIC ELECTROLUMINESCENCE DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 15/896443
[patent_app_country] => US
[patent_app_date] => 2018-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11541
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15896443
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/896443 | Organic electroluminescence display device having a polarizer comprised of polarization regions | Feb 13, 2018 | Issued |
Array
(
[id] => 15641605
[patent_doc_number] => 10593815
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-03-17
[patent_title] => Double layered transparent conductive oxide for reduced Schottky barrier in photovoltaic devices
[patent_app_type] => utility
[patent_app_number] => 15/894690
[patent_app_country] => US
[patent_app_date] => 2018-02-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 4416
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15894690
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/894690 | Double layered transparent conductive oxide for reduced Schottky barrier in photovoltaic devices | Feb 11, 2018 | Issued |
Array
(
[id] => 16234087
[patent_doc_number] => 10741651
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-08-11
[patent_title] => IGBT with improved terminal and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 15/892249
[patent_app_country] => US
[patent_app_date] => 2018-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 5423
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15892249
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/892249 | IGBT with improved terminal and manufacturing method thereof | Feb 7, 2018 | Issued |
Array
(
[id] => 14631335
[patent_doc_number] => 20190229037
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-07-25
[patent_title] => MULTI-LAYER COOLING STRUCTURE INCLUDING THROUGH-SILICON VIAS THROUGH A PLURALITY OF DIRECTLY-BONDED SUBSTRATES AND METHODS OF MAKING THE SAME
[patent_app_type] => utility
[patent_app_number] => 15/879183
[patent_app_country] => US
[patent_app_date] => 2018-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7278
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15879183
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/879183 | Multi-layer cooling structure including through-silicon vias through a plurality of directly-bonded substrates and methods of making the same | Jan 23, 2018 | Issued |
Array
(
[id] => 14859515
[patent_doc_number] => 10418494
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-09-17
[patent_title] => Method of manufacturing semiconductor device
[patent_app_type] => utility
[patent_app_number] => 15/867242
[patent_app_country] => US
[patent_app_date] => 2018-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 23
[patent_no_of_words] => 6917
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 285
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15867242
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/867242 | Method of manufacturing semiconductor device | Jan 9, 2018 | Issued |
Array
(
[id] => 14569987
[patent_doc_number] => 20190212600
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-07-11
[patent_title] => DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 15/863104
[patent_app_country] => US
[patent_app_date] => 2018-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5459
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15863104
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/863104 | Display device | Jan 4, 2018 | Issued |
Array
(
[id] => 14542789
[patent_doc_number] => 20190207016
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-07-04
[patent_title] => METHOD FOR FABRICATING OF AT LEAST A FIELD-EFFECT TRANSISTOR
[patent_app_type] => utility
[patent_app_number] => 15/858266
[patent_app_country] => US
[patent_app_date] => 2017-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13158
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 233
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15858266
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/858266 | Method of manufacturing at least one field effect transistor having epitaxially grown electrodes | Dec 28, 2017 | Issued |