
Gbemileke J. Onamuti
Examiner (ID: 296, Phone: (571)270-5619 , Office: P/2463 )
| Most Active Art Unit | 2463 |
| Art Unit(s) | 2416, 2463 |
| Total Applications | 897 |
| Issued Applications | 769 |
| Pending Applications | 40 |
| Abandoned Applications | 113 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5076940
[patent_doc_number] => 20070120164
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-05-31
[patent_title] => 'FILM FORMING METHOD AND OXIDE THIN FILM ELEMENT'
[patent_app_type] => utility
[patent_app_number] => 11/551122
[patent_app_country] => US
[patent_app_date] => 2006-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 6819
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0120/20070120164.pdf
[firstpage_image] =>[orig_patent_app_number] => 11551122
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/551122 | FILM FORMING METHOD AND OXIDE THIN FILM ELEMENT | Oct 18, 2006 | Abandoned |
Array
(
[id] => 5912988
[patent_doc_number] => 20060128050
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-15
[patent_title] => 'Methods of fabricating image sensors including local interconnections'
[patent_app_type] => utility
[patent_app_number] => 11/348642
[patent_app_country] => US
[patent_app_date] => 2006-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 7196
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0128/20060128050.pdf
[firstpage_image] =>[orig_patent_app_number] => 11348642
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/348642 | Methods of fabricating image sensors including local interconnections | Feb 6, 2006 | Issued |
Array
(
[id] => 5713315
[patent_doc_number] => 20060076678
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-04-13
[patent_title] => 'Thick metal layer integrated process flow to improve power delivery and mechanical buffering'
[patent_app_type] => utility
[patent_app_number] => 11/281709
[patent_app_country] => US
[patent_app_date] => 2005-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 3874
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0076/20060076678.pdf
[firstpage_image] =>[orig_patent_app_number] => 11281709
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/281709 | Thick metal layer integrated process flow to improve power delivery and mechanical buffering | Nov 15, 2005 | Abandoned |
Array
(
[id] => 5763170
[patent_doc_number] => 20060017109
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-26
[patent_title] => 'High voltage ESD-protection structure'
[patent_app_type] => utility
[patent_app_number] => 11/201373
[patent_app_country] => US
[patent_app_date] => 2005-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2943
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0017/20060017109.pdf
[firstpage_image] =>[orig_patent_app_number] => 11201373
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/201373 | High voltage ESD-protection structure | Aug 9, 2005 | Issued |
Array
(
[id] => 521382
[patent_doc_number] => 07186594
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-03-06
[patent_title] => 'High voltage ESD-protection structure'
[patent_app_type] => utility
[patent_app_number] => 11/183640
[patent_app_country] => US
[patent_app_date] => 2005-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3000
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 215
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/186/07186594.pdf
[firstpage_image] =>[orig_patent_app_number] => 11183640
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/183640 | High voltage ESD-protection structure | Jul 17, 2005 | Issued |
Array
(
[id] => 7045715
[patent_doc_number] => 20050250310
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-11-10
[patent_title] => 'Multi-layer interconnection circuit module and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/166970
[patent_app_country] => US
[patent_app_date] => 2005-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 8426
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0250/20050250310.pdf
[firstpage_image] =>[orig_patent_app_number] => 11166970
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/166970 | Multi-layer interconnection circuit module and manufacturing method thereof | Jun 23, 2005 | Issued |
Array
(
[id] => 7165074
[patent_doc_number] => 20050201139
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-15
[patent_title] => 'Memory Device'
[patent_app_type] => utility
[patent_app_number] => 11/121011
[patent_app_country] => US
[patent_app_date] => 2005-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4123
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0201/20050201139.pdf
[firstpage_image] =>[orig_patent_app_number] => 11121011
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/121011 | Memory Device | May 3, 2005 | Abandoned |
Array
(
[id] => 535653
[patent_doc_number] => 07180136
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-02-20
[patent_title] => 'Biased, triple-well fully depleted SOI structure'
[patent_app_type] => utility
[patent_app_number] => 11/111409
[patent_app_country] => US
[patent_app_date] => 2005-04-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 7253
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/180/07180136.pdf
[firstpage_image] =>[orig_patent_app_number] => 11111409
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/111409 | Biased, triple-well fully depleted SOI structure | Apr 20, 2005 | Issued |
Array
(
[id] => 521369
[patent_doc_number] => 07186592
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-03-06
[patent_title] => 'High performance, integrated, MOS-type semiconductor device and related manufacturing process'
[patent_app_type] => utility
[patent_app_number] => 11/103772
[patent_app_country] => US
[patent_app_date] => 2005-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 3097
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/186/07186592.pdf
[firstpage_image] =>[orig_patent_app_number] => 11103772
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/103772 | High performance, integrated, MOS-type semiconductor device and related manufacturing process | Apr 11, 2005 | Issued |
Array
(
[id] => 521302
[patent_doc_number] => 07186584
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-03-06
[patent_title] => 'Integrated circuit chip, electronic device and method of manufacturing the same, and electronic instrument'
[patent_app_type] => utility
[patent_app_number] => 11/099390
[patent_app_country] => US
[patent_app_date] => 2005-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 24
[patent_no_of_words] => 10340
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/186/07186584.pdf
[firstpage_image] =>[orig_patent_app_number] => 11099390
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/099390 | Integrated circuit chip, electronic device and method of manufacturing the same, and electronic instrument | Apr 3, 2005 | Issued |
Array
(
[id] => 6944840
[patent_doc_number] => 20050196889
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-08
[patent_title] => 'Methods of fabricating image sensors including local interconnections'
[patent_app_type] => utility
[patent_app_number] => 11/095385
[patent_app_country] => US
[patent_app_date] => 2005-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 7159
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0196/20050196889.pdf
[firstpage_image] =>[orig_patent_app_number] => 11095385
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/095385 | Methods of fabricating image sensors including local interconnections | Mar 30, 2005 | Issued |
Array
(
[id] => 400769
[patent_doc_number] => 07296245
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-11-13
[patent_title] => 'Combined e-beam and optical exposure semiconductor lithography'
[patent_app_type] => utility
[patent_app_number] => 11/080316
[patent_app_country] => US
[patent_app_date] => 2005-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 13
[patent_no_of_words] => 3597
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/296/07296245.pdf
[firstpage_image] =>[orig_patent_app_number] => 11080316
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/080316 | Combined e-beam and optical exposure semiconductor lithography | Mar 13, 2005 | Issued |
Array
(
[id] => 475075
[patent_doc_number] => 07226816
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-06-05
[patent_title] => 'Method of forming connection and anti-fuse in layered substrate such as SOI'
[patent_app_type] => utility
[patent_app_number] => 11/055106
[patent_app_country] => US
[patent_app_date] => 2005-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 18
[patent_no_of_words] => 4843
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/226/07226816.pdf
[firstpage_image] =>[orig_patent_app_number] => 11055106
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/055106 | Method of forming connection and anti-fuse in layered substrate such as SOI | Feb 10, 2005 | Issued |
Array
(
[id] => 7037940
[patent_doc_number] => 20050157374
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-21
[patent_title] => 'Microelectromechanical device packages with integral heaters'
[patent_app_type] => utility
[patent_app_number] => 11/043507
[patent_app_country] => US
[patent_app_date] => 2005-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 6628
[patent_no_of_claims] => 83
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0157/20050157374.pdf
[firstpage_image] =>[orig_patent_app_number] => 11043507
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/043507 | Microelectromechanical device packages with integral heaters | Jan 24, 2005 | Issued |
Array
(
[id] => 7169291
[patent_doc_number] => 20050121805
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-09
[patent_title] => 'Semiconductor device and a method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/035999
[patent_app_country] => US
[patent_app_date] => 2005-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 8408
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0121/20050121805.pdf
[firstpage_image] =>[orig_patent_app_number] => 11035999
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/035999 | Semiconductor device and a method of manufacturing the same | Jan 17, 2005 | Abandoned |
Array
(
[id] => 463374
[patent_doc_number] => 07238603
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-07-03
[patent_title] => 'Connecting member between wiring films, manufacturing method thereof, and manufacturing method of multilayer wiring substrate'
[patent_app_type] => utility
[patent_app_number] => 11/029423
[patent_app_country] => US
[patent_app_date] => 2005-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 99
[patent_no_of_words] => 15754
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/238/07238603.pdf
[firstpage_image] =>[orig_patent_app_number] => 11029423
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/029423 | Connecting member between wiring films, manufacturing method thereof, and manufacturing method of multilayer wiring substrate | Jan 5, 2005 | Issued |
Array
(
[id] => 6981183
[patent_doc_number] => 20050151251
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-14
[patent_title] => 'Mounting substrate and electronic component using the same'
[patent_app_type] => utility
[patent_app_number] => 11/013698
[patent_app_country] => US
[patent_app_date] => 2004-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 3691
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0151/20050151251.pdf
[firstpage_image] =>[orig_patent_app_number] => 11013698
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/013698 | Mounting substrate and electronic component using the same | Dec 16, 2004 | Abandoned |
Array
(
[id] => 5913010
[patent_doc_number] => 20060128072
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-15
[patent_title] => 'Method of protecting fuses in an integrated circuit die'
[patent_app_type] => utility
[patent_app_number] => 11/011459
[patent_app_country] => US
[patent_app_date] => 2004-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2001
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0128/20060128072.pdf
[firstpage_image] =>[orig_patent_app_number] => 11011459
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/011459 | Method of protecting fuses in an integrated circuit die | Dec 12, 2004 | Abandoned |
Array
(
[id] => 5745745
[patent_doc_number] => 20060108674
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-25
[patent_title] => 'Package structure of memory card and packaging method for the structure'
[patent_app_type] => utility
[patent_app_number] => 10/997508
[patent_app_country] => US
[patent_app_date] => 2004-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 2302
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0108/20060108674.pdf
[firstpage_image] =>[orig_patent_app_number] => 10997508
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/997508 | Package structure of memory card and packaging method for the structure | Nov 23, 2004 | Abandoned |
Array
(
[id] => 5745767
[patent_doc_number] => 20060108697
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-25
[patent_title] => 'Multi-chips semiconductor device assemblies and methods for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 10/995818
[patent_app_country] => US
[patent_app_date] => 2004-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7207
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0108/20060108697.pdf
[firstpage_image] =>[orig_patent_app_number] => 10995818
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/995818 | Multi-chips semiconductor device assemblies and methods for fabricating the same | Nov 21, 2004 | Issued |