Search

Gbemileke J. Onamuti

Examiner (ID: 296, Phone: (571)270-5619 , Office: P/2463 )

Most Active Art Unit
2463
Art Unit(s)
2416, 2463
Total Applications
897
Issued Applications
769
Pending Applications
40
Abandoned Applications
113

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 956233 [patent_doc_number] => 06955983 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-18 [patent_title] => 'Methods of forming metal interconnections of semiconductor devices by treating a barrier metal layer' [patent_app_type] => utility [patent_app_number] => 10/373368 [patent_app_country] => US [patent_app_date] => 2003-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5081 [patent_no_of_claims] => 73 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/955/06955983.pdf [firstpage_image] =>[orig_patent_app_number] => 10373368 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/373368
Methods of forming metal interconnections of semiconductor devices by treating a barrier metal layer Feb 23, 2003 Issued
Array ( [id] => 6704408 [patent_doc_number] => 20030151142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-14 [patent_title] => 'Subresolution features for a semiconductor device' [patent_app_type] => new [patent_app_number] => 10/368959 [patent_app_country] => US [patent_app_date] => 2003-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5296 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20030151142.pdf [firstpage_image] =>[orig_patent_app_number] => 10368959 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/368959
Subresolution features for a semiconductor device Feb 18, 2003 Issued
Array ( [id] => 6794805 [patent_doc_number] => 20030173678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-18 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => new [patent_app_number] => 10/366609 [patent_app_country] => US [patent_app_date] => 2003-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3496 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20030173678.pdf [firstpage_image] =>[orig_patent_app_number] => 10366609 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/366609
Semiconductor device and method for fabricating the same Feb 13, 2003 Abandoned
Array ( [id] => 7415044 [patent_doc_number] => 20040159912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-19 [patent_title] => 'Bipolar transistor for an integrated circuit having variable value emitter ballast resistors' [patent_app_type] => new [patent_app_number] => 10/366158 [patent_app_country] => US [patent_app_date] => 2003-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4918 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20040159912.pdf [firstpage_image] =>[orig_patent_app_number] => 10366158 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/366158
Bipolar transistor for an integrated circuit having variable value emitter ballast resistors Feb 12, 2003 Issued
Array ( [id] => 938391 [patent_doc_number] => 06972220 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-06 [patent_title] => 'Structures and methods of anti-fuse formation in SOI' [patent_app_type] => utility [patent_app_number] => 10/366298 [patent_app_country] => US [patent_app_date] => 2003-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 4819 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/972/06972220.pdf [firstpage_image] =>[orig_patent_app_number] => 10366298 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/366298
Structures and methods of anti-fuse formation in SOI Feb 11, 2003 Issued
Array ( [id] => 7343152 [patent_doc_number] => 20040046176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-11 [patent_title] => 'Avalanche phototransistor' [patent_app_type] => new [patent_app_number] => 10/365229 [patent_app_country] => US [patent_app_date] => 2003-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5159 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20040046176.pdf [firstpage_image] =>[orig_patent_app_number] => 10365229 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/365229
Avalanche phototransistor Feb 11, 2003 Abandoned
Array ( [id] => 1172189 [patent_doc_number] => 06753608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-22 [patent_title] => 'Semiconductor device with seal ring' [patent_app_type] => B2 [patent_app_number] => 10/360799 [patent_app_country] => US [patent_app_date] => 2003-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 29 [patent_no_of_words] => 9320 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/753/06753608.pdf [firstpage_image] =>[orig_patent_app_number] => 10360799 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/360799
Semiconductor device with seal ring Feb 9, 2003 Issued
Array ( [id] => 7219882 [patent_doc_number] => 20040155332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-12 [patent_title] => 'Semiconductor die package with reduced inductance and reduced die attach flow out' [patent_app_type] => new [patent_app_number] => 10/364549 [patent_app_country] => US [patent_app_date] => 2003-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6014 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20040155332.pdf [firstpage_image] =>[orig_patent_app_number] => 10364549 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/364549
Semiconductor die package with reduced inductance and reduced die attach flow out Feb 9, 2003 Issued
Array ( [id] => 994003 [patent_doc_number] => 06917104 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-12 [patent_title] => 'Integrated circuit chip, electronic device and method of manufacturing the same, and electronic instrument' [patent_app_type] => utility [patent_app_number] => 10/361839 [patent_app_country] => US [patent_app_date] => 2003-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 24 [patent_no_of_words] => 10299 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/917/06917104.pdf [firstpage_image] =>[orig_patent_app_number] => 10361839 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/361839
Integrated circuit chip, electronic device and method of manufacturing the same, and electronic instrument Feb 9, 2003 Issued
Array ( [id] => 1024590 [patent_doc_number] => 06884709 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-26 [patent_title] => 'Connecting member between wiring films, manufacturing method thereof, and manufacturing method of multilayer wiring substrate' [patent_app_type] => utility [patent_app_number] => 10/358229 [patent_app_country] => US [patent_app_date] => 2003-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 98 [patent_no_of_words] => 15730 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/884/06884709.pdf [firstpage_image] =>[orig_patent_app_number] => 10358229 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/358229
Connecting member between wiring films, manufacturing method thereof, and manufacturing method of multilayer wiring substrate Feb 4, 2003 Issued
Array ( [id] => 1132128 [patent_doc_number] => 06787785 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-07 [patent_title] => 'Mask and production method therefor and production method for semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/343701 [patent_app_country] => US [patent_app_date] => 2003-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 44 [patent_no_of_words] => 10426 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 629 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/787/06787785.pdf [firstpage_image] =>[orig_patent_app_number] => 10343701 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/343701
Mask and production method therefor and production method for semiconductor device Feb 2, 2003 Issued
Array ( [id] => 6787782 [patent_doc_number] => 20030139021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-24 [patent_title] => 'Methods of wafer level fabrication and assembly of chip scale packages' [patent_app_type] => new [patent_app_number] => 10/357656 [patent_app_country] => US [patent_app_date] => 2003-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3477 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20030139021.pdf [firstpage_image] =>[orig_patent_app_number] => 10357656 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/357656
Methods of wafer level fabrication and assembly of chip scale packages Feb 2, 2003 Issued
Array ( [id] => 6830008 [patent_doc_number] => 20030181066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-25 [patent_title] => 'Method to produce a porous oxygen-silicon layer' [patent_app_type] => new [patent_app_number] => 10/357278 [patent_app_country] => US [patent_app_date] => 2003-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3374 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20030181066.pdf [firstpage_image] =>[orig_patent_app_number] => 10357278 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/357278
Method to produce a porous oxygen-silicon layer Jan 29, 2003 Abandoned
Array ( [id] => 1059480 [patent_doc_number] => 06852570 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-08 [patent_title] => 'Method of manufacturing a stacked semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/346066 [patent_app_country] => US [patent_app_date] => 2003-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 16 [patent_no_of_words] => 3342 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/852/06852570.pdf [firstpage_image] =>[orig_patent_app_number] => 10346066 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/346066
Method of manufacturing a stacked semiconductor device Jan 16, 2003 Issued
Array ( [id] => 609908 [patent_doc_number] => 07151292 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-12-19 [patent_title] => 'Dielectric memory cell structure with counter doped channel region' [patent_app_type] => utility [patent_app_number] => 10/342549 [patent_app_country] => US [patent_app_date] => 2003-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5293 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/151/07151292.pdf [firstpage_image] =>[orig_patent_app_number] => 10342549 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/342549
Dielectric memory cell structure with counter doped channel region Jan 14, 2003 Issued
Array ( [id] => 1196650 [patent_doc_number] => 06727141 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-27 [patent_title] => 'DRAM having offset vertical transistors and method' [patent_app_type] => B1 [patent_app_number] => 10/342419 [patent_app_country] => US [patent_app_date] => 2003-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2287 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/727/06727141.pdf [firstpage_image] =>[orig_patent_app_number] => 10342419 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/342419
DRAM having offset vertical transistors and method Jan 13, 2003 Issued
Array ( [id] => 7380046 [patent_doc_number] => 20040036104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-26 [patent_title] => 'Semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/341359 [patent_app_country] => US [patent_app_date] => 2003-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9271 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20040036104.pdf [firstpage_image] =>[orig_patent_app_number] => 10341359 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/341359
Semiconductor memory device Jan 13, 2003 Issued
Array ( [id] => 6807317 [patent_doc_number] => 20030197256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-23 [patent_title] => 'Power conditioning substrate stiffener' [patent_app_type] => new [patent_app_number] => 10/341906 [patent_app_country] => US [patent_app_date] => 2003-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1959 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20030197256.pdf [firstpage_image] =>[orig_patent_app_number] => 10341906 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/341906
Power conditioning substrate stiffener Jan 12, 2003 Abandoned
Array ( [id] => 7318895 [patent_doc_number] => 20040135218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'MOS transistor with high k gate dielectric' [patent_app_type] => new [patent_app_number] => 10/341646 [patent_app_country] => US [patent_app_date] => 2003-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1995 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20040135218.pdf [firstpage_image] =>[orig_patent_app_number] => 10341646 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/341646
MOS transistor with high k gate dielectric Jan 12, 2003 Abandoned
Array ( [id] => 6785777 [patent_doc_number] => 20030137016 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-24 [patent_title] => 'Lateral power MOSFET for high switching speeds' [patent_app_type] => new [patent_app_number] => 10/340040 [patent_app_country] => US [patent_app_date] => 2003-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2734 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0137/20030137016.pdf [firstpage_image] =>[orig_patent_app_number] => 10340040 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/340040
Lateral power MOSFET for high switching speeds Jan 9, 2003 Issued
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