Geepy Pe

Array ( [id] => 4050586 [patent_doc_number] => 05943581 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Method of fabricating a buried reservoir capacitor structure for high-density dynamic random access memory (DRAM) circuits' [patent_app_type] => 1 [patent_app_number] => 8/964808 [patent_app_country] => US [patent_app_date] => 1997-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 5242 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943581.pdf [firstpage_image] =>[orig_patent_app_number] => 964808 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4031086 [patent_doc_number] => 05963814 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Method of forming recessed container cells by wet etching conductive layer and dissimilar layer formed over conductive layer' [patent_app_type] => 1 [patent_app_number] => 8/959379 [patent_app_country] => US [patent_app_date] => 1997-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3866 [patent_no_of_claims] => 103 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963814.pdf [firstpage_image] =>[orig_patent_app_number] => 959379 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3994007 [patent_doc_number] => 05985738 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Method for forming field oxide of semiconductor device using wet and dry oxidation' [patent_app_type] => 1 [patent_app_number] => 8/959205 [patent_app_country] => US [patent_app_date] => 1997-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 2781 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/985/05985738.pdf [firstpage_image] =>[orig_patent_app_number] => 959205 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3937620 [patent_doc_number] => 05981359 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Method of manufacturing semiconductor device having isolation film on SOI substrate' [patent_app_type] => 1 [patent_app_number] => 8/954613 [patent_app_country] => US [patent_app_date] => 1997-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 3182 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/981/05981359.pdf [firstpage_image] =>[orig_patent_app_number] => 954613 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3937242 [patent_doc_number] => 05981332 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Reduced parasitic leakage in semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 8/940237 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4333 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/981/05981332.pdf [firstpage_image] =>[orig_patent_app_number] => 940237 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3953117 [patent_doc_number] => 05940720 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Methods of forming oxide isolation regions for integrated circuits substrates using mask and spacer' [patent_app_type] => 1 [patent_app_number] => 8/920491 [patent_app_country] => US [patent_app_date] => 1997-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2472 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940720.pdf [firstpage_image] =>[orig_patent_app_number] => 920491 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3989662 [patent_doc_number] => 05959325 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Method for forming cornered images on a substrate and photomask formed thereby' [patent_app_type] => 1 [patent_app_number] => 8/917009 [patent_app_country] => US [patent_app_date] => 1997-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 44 [patent_no_of_words] => 8250 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/959/05959325.pdf [firstpage_image] =>[orig_patent_app_number] => 917009 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4056873 [patent_doc_number] => 05895224 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Three-dimensional cavity surface emitting laser structure and fabrication method thereof' [patent_app_type] => 1 [patent_app_number] => 8/915298 [patent_app_country] => US [patent_app_date] => 1997-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 1980 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/895/05895224.pdf [firstpage_image] =>[orig_patent_app_number] => 915298 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4059008 [patent_doc_number] => 05913136 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Process for making a transistor with self-aligned source and drain contacts' [patent_app_type] => 1 [patent_app_number] => 8/911146 [patent_app_country] => US [patent_app_date] => 1997-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 4811 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/913/05913136.pdf [firstpage_image] =>[orig_patent_app_number] => 911146 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3935285 [patent_doc_number] => 05972777 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Method of forming isolation by nitrogen implant to reduce bird\'s beak' [patent_app_type] => 1 [patent_app_number] => 8/898973 [patent_app_country] => US [patent_app_date] => 1997-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 1935 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/972/05972777.pdf [firstpage_image] =>[orig_patent_app_number] => 898973 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4004378 [patent_doc_number] => 05960297 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Shallow trench isolation structure and method of forming the same' [patent_app_type] => 1 [patent_app_number] => 8/887137 [patent_app_country] => US [patent_app_date] => 1997-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 43 [patent_no_of_words] => 5271 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/960/05960297.pdf [firstpage_image] =>[orig_patent_app_number] => 887137 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4031016 [patent_doc_number] => 05963809 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Asymmetrical MOSFET with gate pattern after source/drain formation' [patent_app_type] => 1 [patent_app_number] => 8/883511 [patent_app_country] => US [patent_app_date] => 1997-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 6145 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963809.pdf [firstpage_image] =>[orig_patent_app_number] => 883511 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3937377 [patent_doc_number] => 05981342 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Method of making a semiconductor component with compensation implantation' [patent_app_type] => 1 [patent_app_number] => 8/858819 [patent_app_country] => US [patent_app_date] => 1997-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 3499 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/981/05981342.pdf [firstpage_image] =>[orig_patent_app_number] => 858819 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3896616 [patent_doc_number] => 05897364 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Method of forming N- and P-channel transistors with shallow junctions' [patent_app_type] => 1 [patent_app_number] => 8/668711 [patent_app_country] => US [patent_app_date] => 1996-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 1653 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/897/05897364.pdf [firstpage_image] =>[orig_patent_app_number] => 668711 [rel_patent_id] =>[rel_patent_doc_number] =>)