| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[patent_issue_date] => 1998-03-24
[patent_title] => 'Four-phase driving CCD solid-state imaging device with a two-layer transfer gate electrode'
[patent_app_type] => 1
[patent_app_number] => 8/769380
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Array
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[patent_doc_number] => 05895959
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-20
[patent_title] => 'Input port electrostatic discharge protection circuit for an intergrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/770168
[patent_app_country] => US
[patent_app_date] => 1996-12-19
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[firstpage_image] =>[orig_patent_app_number] => 770168
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/770168 | Input port electrostatic discharge protection circuit for an intergrated circuit | Dec 18, 1996 | Issued |
Array
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[id] => 3747528
[patent_doc_number] => 05786724
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-28
[patent_title] => 'Control of body effect in MOS transistors by switching source-to-body bias'
[patent_app_type] => 1
[patent_app_number] => 8/768876
[patent_app_country] => US
[patent_app_date] => 1996-12-17
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/786/05786724.pdf
[firstpage_image] =>[orig_patent_app_number] => 768876
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/768876 | Control of body effect in MOS transistors by switching source-to-body bias | Dec 16, 1996 | Issued |
| 08/764204 | MOSFET WITH SIDEWALL SPACER ON GATE SECTION | Dec 12, 1996 | Abandoned |
Array
(
[id] => 3999261
[patent_doc_number] => 05920111
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-06
[patent_title] => 'CMOS OP-AMP circuit using BJT as input stage'
[patent_app_type] => 1
[patent_app_number] => 8/763994
[patent_app_country] => US
[patent_app_date] => 1996-12-12
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[pdf_file] => patents/05/920/05920111.pdf
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Array
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[id] => 3844984
[patent_doc_number] => 05847428
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-08
[patent_title] => 'Integrated circuit gate conductor which uses layered spacers to produce a graded junction'
[patent_app_type] => 1
[patent_app_number] => 8/761132
[patent_app_country] => US
[patent_app_date] => 1996-12-06
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[firstpage_image] =>[orig_patent_app_number] => 761132
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/761132 | Integrated circuit gate conductor which uses layered spacers to produce a graded junction | Dec 5, 1996 | Issued |
Array
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[id] => 3903740
[patent_doc_number] => 05751038
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[patent_kind] => NA
[patent_issue_date] => 1998-05-12
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[patent_app_type] => 1
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Array
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[patent_doc_number] => 05828107
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[patent_issue_date] => 1998-10-27
[patent_title] => 'Semiconductor integrated circuit device'
[patent_app_type] => 1
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[pdf_file] => patents/05/828/05828107.pdf
[firstpage_image] =>[orig_patent_app_number] => 748495
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/748495 | Semiconductor integrated circuit device | Nov 7, 1996 | Issued |
Array
(
[id] => 4048759
[patent_doc_number] => 05874755
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-23
[patent_title] => 'Ferroelectric semiconductor device and method of manufacture'
[patent_app_type] => 1
[patent_app_number] => 8/743768
[patent_app_country] => US
[patent_app_date] => 1996-11-07
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 743768
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/743768 | Ferroelectric semiconductor device and method of manufacture | Nov 6, 1996 | Issued |
| 08/745136 | INPUT/OUTPUT PROTECTION CIRCUIT HAVING AN SOI STRUCTURE | Nov 6, 1996 | Abandoned |
Array
(
[id] => 3891603
[patent_doc_number] => 05714786
[patent_country] => US
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[patent_issue_date] => 1998-02-03
[patent_title] => 'Transistors having controlled conductive spacers, uses of such transistors and methods of making such transistors'
[patent_app_type] => 1
[patent_app_number] => 8/741828
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/741828 | Transistors having controlled conductive spacers, uses of such transistors and methods of making such transistors | Oct 30, 1996 | Issued |
Array
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[patent_issue_date] => 1998-07-21
[patent_title] => 'Non-single crystalline semiconductor photo detector with super lattice'
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[firstpage_image] =>[orig_patent_app_number] => 739194
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/739194 | Non-single crystalline semiconductor photo detector with super lattice | Oct 29, 1996 | Issued |
Array
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[patent_issue_date] => 1998-12-08
[patent_title] => 'Semiconductor photo detector containing crystalline amplification layer'
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[patent_app_number] => 8/739198
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[firstpage_image] =>[orig_patent_app_number] => 739198
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/739198 | Semiconductor photo detector containing crystalline amplification layer | Oct 29, 1996 | Issued |
Array
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Array
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