Search

Gene M. Munson

Examiner (ID: 14220)

Most Active Art Unit
2503
Art Unit(s)
2503, 2508, 2506, 2811, 2504
Total Applications
1069
Issued Applications
864
Pending Applications
9
Abandoned Applications
196

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3829967 [patent_doc_number] => 05731601 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-24 [patent_title] => 'Four-phase driving CCD solid-state imaging device with a two-layer transfer gate electrode' [patent_app_type] => 1 [patent_app_number] => 8/769380 [patent_app_country] => US [patent_app_date] => 1996-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 27 [patent_no_of_words] => 4032 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/731/05731601.pdf [firstpage_image] =>[orig_patent_app_number] => 769380 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/769380
Four-phase driving CCD solid-state imaging device with a two-layer transfer gate electrode Dec 18, 1996 Issued
Array ( [id] => 4067834 [patent_doc_number] => 05895959 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Input port electrostatic discharge protection circuit for an intergrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/770168 [patent_app_country] => US [patent_app_date] => 1996-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3133 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/895/05895959.pdf [firstpage_image] =>[orig_patent_app_number] => 770168 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/770168
Input port electrostatic discharge protection circuit for an intergrated circuit Dec 18, 1996 Issued
Array ( [id] => 3747528 [patent_doc_number] => 05786724 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Control of body effect in MOS transistors by switching source-to-body bias' [patent_app_type] => 1 [patent_app_number] => 8/768876 [patent_app_country] => US [patent_app_date] => 1996-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 4148 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/786/05786724.pdf [firstpage_image] =>[orig_patent_app_number] => 768876 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/768876
Control of body effect in MOS transistors by switching source-to-body bias Dec 16, 1996 Issued
08/764204 MOSFET WITH SIDEWALL SPACER ON GATE SECTION Dec 12, 1996 Abandoned
Array ( [id] => 3999261 [patent_doc_number] => 05920111 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'CMOS OP-AMP circuit using BJT as input stage' [patent_app_type] => 1 [patent_app_number] => 8/763994 [patent_app_country] => US [patent_app_date] => 1996-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 2372 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 379 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920111.pdf [firstpage_image] =>[orig_patent_app_number] => 763994 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/763994
CMOS OP-AMP circuit using BJT as input stage Dec 11, 1996 Issued
Array ( [id] => 3844984 [patent_doc_number] => 05847428 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Integrated circuit gate conductor which uses layered spacers to produce a graded junction' [patent_app_type] => 1 [patent_app_number] => 8/761132 [patent_app_country] => US [patent_app_date] => 1996-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 6718 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/847/05847428.pdf [firstpage_image] =>[orig_patent_app_number] => 761132 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/761132
Integrated circuit gate conductor which uses layered spacers to produce a graded junction Dec 5, 1996 Issued
Array ( [id] => 3903740 [patent_doc_number] => 05751038 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Electrically erasable and programmable read only memory (EEPROM) having multiple overlapping metallization layers' [patent_app_type] => 1 [patent_app_number] => 8/753554 [patent_app_country] => US [patent_app_date] => 1996-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3108 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/751/05751038.pdf [firstpage_image] =>[orig_patent_app_number] => 753554 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/753554
Electrically erasable and programmable read only memory (EEPROM) having multiple overlapping metallization layers Nov 25, 1996 Issued
Array ( [id] => 3801944 [patent_doc_number] => 05828107 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 8/748495 [patent_app_country] => US [patent_app_date] => 1996-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3731 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828107.pdf [firstpage_image] =>[orig_patent_app_number] => 748495 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/748495
Semiconductor integrated circuit device Nov 7, 1996 Issued
Array ( [id] => 4048759 [patent_doc_number] => 05874755 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Ferroelectric semiconductor device and method of manufacture' [patent_app_type] => 1 [patent_app_number] => 8/743768 [patent_app_country] => US [patent_app_date] => 1996-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1561 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/874/05874755.pdf [firstpage_image] =>[orig_patent_app_number] => 743768 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/743768
Ferroelectric semiconductor device and method of manufacture Nov 6, 1996 Issued
08/745136 INPUT/OUTPUT PROTECTION CIRCUIT HAVING AN SOI STRUCTURE Nov 6, 1996 Abandoned
Array ( [id] => 3891603 [patent_doc_number] => 05714786 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-03 [patent_title] => 'Transistors having controlled conductive spacers, uses of such transistors and methods of making such transistors' [patent_app_type] => 1 [patent_app_number] => 8/741828 [patent_app_country] => US [patent_app_date] => 1996-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3245 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/714/05714786.pdf [firstpage_image] =>[orig_patent_app_number] => 741828 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/741828
Transistors having controlled conductive spacers, uses of such transistors and methods of making such transistors Oct 30, 1996 Issued
Array ( [id] => 3830830 [patent_doc_number] => 05783838 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Non-single crystalline semiconductor photo detector with super lattice' [patent_app_type] => 1 [patent_app_number] => 8/739194 [patent_app_country] => US [patent_app_date] => 1996-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 27 [patent_no_of_words] => 9982 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/783/05783838.pdf [firstpage_image] =>[orig_patent_app_number] => 739194 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/739194
Non-single crystalline semiconductor photo detector with super lattice Oct 29, 1996 Issued
Array ( [id] => 3844844 [patent_doc_number] => 05847418 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Semiconductor photo detector containing crystalline amplification layer' [patent_app_type] => 1 [patent_app_number] => 8/739198 [patent_app_country] => US [patent_app_date] => 1996-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 24 [patent_no_of_words] => 13529 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/847/05847418.pdf [firstpage_image] =>[orig_patent_app_number] => 739198 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/739198
Semiconductor photo detector containing crystalline amplification layer Oct 29, 1996 Issued
Array ( [id] => 1427231 [patent_doc_number] => 06510193 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-21 [patent_title] => 'Charge transfer device and a semiconductor circuit including the device' [patent_app_type] => B1 [patent_app_number] => 08/739786 [patent_app_country] => US [patent_app_date] => 1996-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 26 [patent_no_of_words] => 8548 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/510/06510193.pdf [firstpage_image] =>[orig_patent_app_number] => 08739786 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/739786
Charge transfer device and a semiconductor circuit including the device Oct 29, 1996 Issued
Array ( [id] => 1522263 [patent_doc_number] => 06414359 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Six transistor SRAM cell having offset p-channel and n-channel transistors' [patent_app_type] => B1 [patent_app_number] => 08/733586 [patent_app_country] => US [patent_app_date] => 1996-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3156 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/414/06414359.pdf [firstpage_image] =>[orig_patent_app_number] => 08733586 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/733586
Six transistor SRAM cell having offset p-channel and n-channel transistors Oct 17, 1996 Issued
Array ( [id] => 3964307 [patent_doc_number] => 05900646 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Method of preventing deterioration of film quality of transparent conductive film a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/730662 [patent_app_country] => US [patent_app_date] => 1996-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 48 [patent_no_of_words] => 9587 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/900/05900646.pdf [firstpage_image] =>[orig_patent_app_number] => 730662 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/730662
Method of preventing deterioration of film quality of transparent conductive film a semiconductor device Oct 10, 1996 Issued
Array ( [id] => 3794244 [patent_doc_number] => 05841154 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'Light-emitting diode device with reduced scatter' [patent_app_type] => 1 [patent_app_number] => 8/731376 [patent_app_country] => US [patent_app_date] => 1996-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4987 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/841/05841154.pdf [firstpage_image] =>[orig_patent_app_number] => 731376 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/731376
Light-emitting diode device with reduced scatter Oct 9, 1996 Issued
Array ( [id] => 3966189 [patent_doc_number] => 05900769 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Two-dimensional CCD having storage cells for withdrawing charge packets from transfer channels during horizontal scan periods' [patent_app_type] => 1 [patent_app_number] => 8/725764 [patent_app_country] => US [patent_app_date] => 1996-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 6735 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/900/05900769.pdf [firstpage_image] =>[orig_patent_app_number] => 725764 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/725764
Two-dimensional CCD having storage cells for withdrawing charge packets from transfer channels during horizontal scan periods Oct 3, 1996 Issued
Array ( [id] => 3780195 [patent_doc_number] => 05757052 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'Bipolar transistor and method of forming BiCMOS circuitry' [patent_app_type] => 1 [patent_app_number] => 8/696244 [patent_app_country] => US [patent_app_date] => 1996-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3242 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/757/05757052.pdf [firstpage_image] =>[orig_patent_app_number] => 696244 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/696244
Bipolar transistor and method of forming BiCMOS circuitry Aug 12, 1996 Issued
Array ( [id] => 3745068 [patent_doc_number] => 05753938 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-19 [patent_title] => 'Static-induction transistors having heterojunction gates and methods of forming same' [patent_app_type] => 1 [patent_app_number] => 8/694276 [patent_app_country] => US [patent_app_date] => 1996-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5142 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/753/05753938.pdf [firstpage_image] =>[orig_patent_app_number] => 694276 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/694276
Static-induction transistors having heterojunction gates and methods of forming same Aug 7, 1996 Issued
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