Search

Gene Nghia Auduong

Examiner (ID: 2491)

Most Active Art Unit
2827
Art Unit(s)
2827, 2712, 2818, 2825
Total Applications
1939
Issued Applications
1863
Pending Applications
12
Abandoned Applications
67

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12162225 [patent_doc_number] => 20180033491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-01 [patent_title] => 'METHOD AND APPARATUS WITH BACKGROUND REFERENCE POSITIONING AND LOCAL REFERENCE POSITIONING' [patent_app_type] => utility [patent_app_number] => 15/655639 [patent_app_country] => US [patent_app_date] => 2017-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 16153 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15655639 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/655639
Background reference positioning and local reference positioning using threshold voltage shift read Jul 19, 2017 Issued
Array ( [id] => 12122112 [patent_doc_number] => 20180005698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/639411 [patent_app_country] => US [patent_app_date] => 2017-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11761 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15639411 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/639411
Memory device Jun 29, 2017 Issued
Array ( [id] => 12554256 [patent_doc_number] => 10014310 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-07-03 [patent_title] => Memory cell structure and operation method thereof [patent_app_type] => utility [patent_app_number] => 15/638377 [patent_app_country] => US [patent_app_date] => 2017-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3228 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15638377 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/638377
Memory cell structure and operation method thereof Jun 29, 2017 Issued
Array ( [id] => 12497904 [patent_doc_number] => 09997257 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-06-12 [patent_title] => Semiconductor device and semiconductor system including the same [patent_app_type] => utility [patent_app_number] => 15/634543 [patent_app_country] => US [patent_app_date] => 2017-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5049 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15634543 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/634543
Semiconductor device and semiconductor system including the same Jun 26, 2017 Issued
Array ( [id] => 12668182 [patent_doc_number] => 20180114560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-26 [patent_title] => NONVOLATILE MEMORY DEVICE AND METHOD OF WRITING SIGNAL IN NONVOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/632113 [patent_app_country] => US [patent_app_date] => 2017-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10493 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15632113 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/632113
Nonvolatile memory device having ferroelectric memory element and resistive memory element and method of writing signal in nonvolatile memory device having the same Jun 22, 2017 Issued
Array ( [id] => 12738256 [patent_doc_number] => 20180137919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-17 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 15/628755 [patent_app_country] => US [patent_app_date] => 2017-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15251 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15628755 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/628755
Semiconductor memory device and method of operating the same Jun 20, 2017 Issued
Array ( [id] => 13005597 [patent_doc_number] => 10026469 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-17 [patent_title] => Semiconductor device performing write operation and write leveling operation [patent_app_type] => utility [patent_app_number] => 15/628889 [patent_app_country] => US [patent_app_date] => 2017-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6149 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15628889 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/628889
Semiconductor device performing write operation and write leveling operation Jun 20, 2017 Issued
Array ( [id] => 11959181 [patent_doc_number] => 20170263333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-14 [patent_title] => 'MULTI-PORT MEMORY, SEMICONDUCTOR DEVICE, AND MEMORY MACRO-CELL' [patent_app_type] => utility [patent_app_number] => 15/606562 [patent_app_country] => US [patent_app_date] => 2017-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10722 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15606562 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/606562
Multi-port memory, semiconductor device, and memory macro-cell capable of performing test in a distributed state May 25, 2017 Issued
Array ( [id] => 11952170 [patent_doc_number] => 20170256321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/598554 [patent_app_country] => US [patent_app_date] => 2017-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10920 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15598554 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/598554
Nonvolatile semiconductor memory device having a control circuit that controls voltage applied to non-selected word lines connected to unselected memory cells May 17, 2017 Issued
Array ( [id] => 12334176 [patent_doc_number] => 09947392 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-04-17 [patent_title] => Memory device sensing circuit [patent_app_type] => utility [patent_app_number] => 15/593892 [patent_app_country] => US [patent_app_date] => 2017-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10592 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15593892 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/593892
Memory device sensing circuit May 11, 2017 Issued
Array ( [id] => 12005160 [patent_doc_number] => 20170309316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-26 [patent_title] => 'APPARATUSES AND METHODS FOR PERFORMING CORNER TURN OPERATIONS USING SENSING CIRCUITRY' [patent_app_type] => utility [patent_app_number] => 15/591899 [patent_app_country] => US [patent_app_date] => 2017-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 24332 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15591899 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/591899
Apparatuses and methods for performing corner turn operations using sensing circuitry May 9, 2017 Issued
Array ( [id] => 11939507 [patent_doc_number] => 20170243657 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-24 [patent_title] => 'MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/588560 [patent_app_country] => US [patent_app_date] => 2017-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 14782 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15588560 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/588560
Semiconductor memory device and writing operation method thereof May 4, 2017 Issued
Array ( [id] => 11869297 [patent_doc_number] => 20170236582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-17 [patent_title] => 'SEMICONDUCTOR APPARATUS COMPRISING A PLURALITY OF CURRENT SINK UNITS' [patent_app_type] => utility [patent_app_number] => 15/583476 [patent_app_country] => US [patent_app_date] => 2017-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11120 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15583476 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/583476
Semiconductor apparatus comprising a plurality of current sink units Apr 30, 2017 Issued
Array ( [id] => 11869298 [patent_doc_number] => 20170236583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-17 [patent_title] => 'SEMICONDUCTOR APPARATUS COMPRISING A PLURALITY OF CURRENT SINK UNITS' [patent_app_type] => utility [patent_app_number] => 15/583543 [patent_app_country] => US [patent_app_date] => 2017-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11120 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15583543 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/583543
Semiconductor apparatus comprising a plurality of current sink units Apr 30, 2017 Issued
Array ( [id] => 11839814 [patent_doc_number] => 20170221534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'SEMICONDUCTOR MEMORY PACKAGE' [patent_app_type] => utility [patent_app_number] => 15/490614 [patent_app_country] => US [patent_app_date] => 2017-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 15526 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15490614 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/490614
Semiconductor memory package including memory device with inverting circuit Apr 17, 2017 Issued
Array ( [id] => 12553479 [patent_doc_number] => 10014048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-03 [patent_title] => Dual interlocked storage cell (DICE) latch sharing active region with neighbor DICE latch and semiconductor device including the same [patent_app_type] => utility [patent_app_number] => 15/486051 [patent_app_country] => US [patent_app_date] => 2017-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3893 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15486051 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/486051
Dual interlocked storage cell (DICE) latch sharing active region with neighbor DICE latch and semiconductor device including the same Apr 11, 2017 Issued
Array ( [id] => 12354546 [patent_doc_number] => 09953692 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-04-24 [patent_title] => Spin orbit torque MRAM memory cell with enhanced thermal stability [patent_app_type] => utility [patent_app_number] => 15/485049 [patent_app_country] => US [patent_app_date] => 2017-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 5413 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15485049 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/485049
Spin orbit torque MRAM memory cell with enhanced thermal stability Apr 10, 2017 Issued
Array ( [id] => 12595131 [patent_doc_number] => 20180090207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-29 [patent_title] => RESISTIVE RANDOM ACCESS MEMORY, MANUFACTURING METHOD THEREOF, AND OPERATION THEREOF [patent_app_type] => utility [patent_app_number] => 15/484137 [patent_app_country] => US [patent_app_date] => 2017-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4040 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15484137 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/484137
Resistive random access memory having charge trapping layer, manufacturing method thereof, and operation thereof Apr 10, 2017 Issued
Array ( [id] => 12019486 [patent_doc_number] => 09812194 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-11-07 [patent_title] => 'Decoding method, memory storage device and memory control circuit unit' [patent_app_type] => utility [patent_app_number] => 15/481473 [patent_app_country] => US [patent_app_date] => 2017-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 13888 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15481473 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/481473
Decoding method, memory storage device and memory control circuit unit Apr 6, 2017 Issued
Array ( [id] => 12631011 [patent_doc_number] => 20180102167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-12 [patent_title] => METHOD FOR PROGRAMMING A NON-VOLATILE MEMORY DEVICE AND A METHOD FOR OPERATING A SYSTEM HAVING THE SAME [patent_app_type] => utility [patent_app_number] => 15/478679 [patent_app_country] => US [patent_app_date] => 2017-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7100 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15478679 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/478679
Method for programming a non-volatile memory device and a method for operating a system having the same Apr 3, 2017 Issued
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