
Gene Nghia Auduong
Examiner (ID: 2491)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2827, 2712, 2818, 2825 |
| Total Applications | 1939 |
| Issued Applications | 1863 |
| Pending Applications | 12 |
| Abandoned Applications | 67 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10624183
[patent_doc_number] => 09343131
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-05-17
[patent_title] => 'Mismatch and noise insensitive sense amplifier circuit for STT MRAM'
[patent_app_type] => utility
[patent_app_number] => 14/629875
[patent_app_country] => US
[patent_app_date] => 2015-02-24
[patent_effective_date] => 0000-00-00
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Array
(
[id] => 14456361
[patent_doc_number] => 10324137
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-06-18
[patent_title] => Intelligent method for calibrating battery capacity
[patent_app_type] => utility
[patent_app_number] => 14/630348
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/630348 | Intelligent method for calibrating battery capacity | Feb 23, 2015 | Issued |
Array
(
[id] => 10277063
[patent_doc_number] => 20150162060
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-06-11
[patent_title] => 'MEMORY MACRO WITH A VOLTAGE KEEPER'
[patent_app_type] => utility
[patent_app_number] => 14/620769
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[patent_app_date] => 2015-02-12
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/620769 | Memory macro with a voltage keeper | Feb 11, 2015 | Issued |
Array
(
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[patent_doc_number] => 09236139
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[patent_kind] => B1
[patent_issue_date] => 2016-01-12
[patent_title] => 'Reduced current program verify in non-volatile memory'
[patent_app_type] => utility
[patent_app_number] => 14/619875
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/619875 | Reduced current program verify in non-volatile memory | Feb 10, 2015 | Issued |
Array
(
[id] => 10261486
[patent_doc_number] => 20150146483
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-05-28
[patent_title] => 'DIFFERENTIAL CURRENT SENSING SCHEME FOR MAGNETIC RANDOM ACCESS MEMORY'
[patent_app_type] => utility
[patent_app_number] => 14/611572
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/611572 | Differential current sensing scheme for magnetic random access memory | Feb 1, 2015 | Issued |
Array
(
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[patent_doc_number] => 20150138883
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[patent_issue_date] => 2015-05-21
[patent_title] => 'NON-VOLATILE SEMICONDUCTOR DEVICE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/607612 | Non-volatile semiconductor device | Jan 27, 2015 | Issued |
Array
(
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[patent_issue_date] => 2015-12-29
[patent_title] => 'Techniques for detection and treating memory hole to local interconnect marginality defects'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/596751 | Techniques for detection and treating memory hole to local interconnect marginality defects | Jan 13, 2015 | Issued |
Array
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[patent_issue_date] => 2015-05-07
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/596639 | Semiconductor memory device having a memory string that includes a transistor having a charge stored therein to indicate the memory string is defective | Jan 13, 2015 | Issued |
Array
(
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[patent_doc_number] => 09466342
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[patent_issue_date] => 2016-10-11
[patent_title] => 'Transistors with source and word line voltage adjusting circuitry for controlling leakage currents and its method thereof'
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[patent_app_number] => 14/593395
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/593395 | Transistors with source and word line voltage adjusting circuitry for controlling leakage currents and its method thereof | Jan 8, 2015 | Issued |
Array
(
[id] => 10666749
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[patent_issue_date] => 2016-01-14
[patent_title] => 'NON-VOLATILE MEMORY AND COLUMN DECODER THEREOF'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/592477 | Non-volatile memory and associated memory array, row decoder, column decoder, write buffer and sensing circuit | Jan 7, 2015 | Issued |
Array
(
[id] => 10232086
[patent_doc_number] => 20150117080
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[patent_issue_date] => 2015-04-30
[patent_title] => 'MULTI-CHIP PACKAGE AND MEMORY SYSTEM'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/590626 | Multi-chip package and memory system | Jan 5, 2015 | Issued |
Array
(
[id] => 10502243
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[patent_title] => 'Apparatus and methods for forming a memory cell using charge monitoring'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/588593 | Apparatus and methods for forming a memory cell using charge monitoring | Jan 1, 2015 | Issued |
Array
(
[id] => 10597091
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[patent_title] => 'DRAM wordline control circuit, DRAM module and method of controlling DRAM wordline voltage'
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Array
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[patent_title] => 'EXTENSIBLE CONFIGURABLE FPGA STORAGE STRUCTURE AND FPGA DEVICE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/758357 | Extensible configurable FPGA storage structure and FPGA device | Dec 29, 2014 | Issued |
Array
(
[id] => 10556841
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[patent_title] => 'Resistive memory write circuitry with bit line drive strength based on storage cell line resistance'
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/578555 | Flash-memory low-speed read mode control circuit | Dec 21, 2014 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/577113 | Bias temperature instability state detection and correction | Dec 18, 2014 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/563605 | Semiconductor memory device | Dec 7, 2014 | Issued |