Gene Nghia Auduong

Array ( [id] => 10899815 [patent_doc_number] => 08923044 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-30 [patent_title] => 'MTP MTJ device' [patent_app_type] => utility [patent_app_number] => 13/589426 [patent_app_country] => US [patent_app_date] => 2012-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 5757 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13589426 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8669993 [patent_doc_number] => 20130044531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-21 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 13/587476 [patent_app_country] => US [patent_app_date] => 2012-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11754 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13587476 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9317703 [patent_doc_number] => 20140050041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-20 [patent_title] => 'DATA STORAGE DEVICE AND CONTROL METHOD FOR NON-VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 13/587158 [patent_app_country] => US [patent_app_date] => 2012-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2416 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13587158 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9650387 [patent_doc_number] => 08804413 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-12 [patent_title] => 'Multi-free layer MTJ and multi-terminal read circuit with concurrent and differential sensing' [patent_app_type] => utility [patent_app_number] => 13/586934 [patent_app_country] => US [patent_app_date] => 2012-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 91 [patent_no_of_words] => 23697 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13586934 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8670001 [patent_doc_number] => 20130044538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-21 [patent_title] => 'STACKED MRAM DEVICE AND MEMORY SYSTEM HAVING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/586976 [patent_app_country] => US [patent_app_date] => 2012-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6426 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13586976 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9346478 [patent_doc_number] => 08665632 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-04 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 13/586170 [patent_app_country] => US [patent_app_date] => 2012-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 10193 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13586170 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8488297 [patent_doc_number] => 20120287704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-15 [patent_title] => 'SPIN CURRENT GENERATOR FOR STT-MRAM OR OTHER SPINTRONICS APPLICATIONS' [patent_app_type] => utility [patent_app_number] => 13/555940 [patent_app_country] => US [patent_app_date] => 2012-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4725 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13555940 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8996549 [patent_doc_number] => 08520446 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-27 [patent_title] => 'Method of erasing a memory including first and second erase modes' [patent_app_type] => utility [patent_app_number] => 13/535922 [patent_app_country] => US [patent_app_date] => 2012-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 7650 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13535922 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8463028 [patent_doc_number] => 20120268196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-25 [patent_title] => 'REGULATORS REGULATING CHARGE PUMP AND MEMORY CIRCUITS THEREOF' [patent_app_type] => utility [patent_app_number] => 13/535034 [patent_app_country] => US [patent_app_date] => 2012-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5029 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13535034 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8463028 [patent_doc_number] => 20120268196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-25 [patent_title] => 'REGULATORS REGULATING CHARGE PUMP AND MEMORY CIRCUITS THEREOF' [patent_app_type] => utility [patent_app_number] => 13/535034 [patent_app_country] => US [patent_app_date] => 2012-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5029 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13535034 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8440817 [patent_doc_number] => 20120257434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-11 [patent_title] => 'CONFIGURABLE BANDWIDTH MEMORY DEVICES AND METHODS' [patent_app_type] => utility [patent_app_number] => 13/524732 [patent_app_country] => US [patent_app_date] => 2012-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3917 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13524732 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8428513 [patent_doc_number] => 20120250388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-04 [patent_title] => 'VARIABLE MEMORY REFRESH DEVICES AND METHODS' [patent_app_type] => utility [patent_app_number] => 13/493651 [patent_app_country] => US [patent_app_date] => 2012-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4274 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13493651 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8392251 [patent_doc_number] => 20120230092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-13 [patent_title] => 'THERMALLY ASSISTED MULTI-BIT MRAM' [patent_app_type] => utility [patent_app_number] => 13/474838 [patent_app_country] => US [patent_app_date] => 2012-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3774 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13474838 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8360820 [patent_doc_number] => 20120215974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-23 [patent_title] => 'MEMORY WITH OUTPUT CONTROL' [patent_app_type] => utility [patent_app_number] => 13/463339 [patent_app_country] => US [patent_app_date] => 2012-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 15512 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13463339 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8360818 [patent_doc_number] => 20120215961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-23 [patent_title] => 'APPARATUS, SYSTEM, AND METHOD FOR BIASING DATA IN A SOLID-STATE STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 13/461628 [patent_app_country] => US [patent_app_date] => 2012-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 32447 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13461628 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9133435 [patent_doc_number] => 20130294149 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-07 [patent_title] => 'REDUCING POWER IN SRAM USING SUPPLY VOLTAGE CONTROL' [patent_app_type] => utility [patent_app_number] => 13/461130 [patent_app_country] => US [patent_app_date] => 2012-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9201 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13461130 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8475817 [patent_doc_number] => 20120275224 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-01 [patent_title] => 'OPERATING METHOD OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/455558 [patent_app_country] => US [patent_app_date] => 2012-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6221 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13455558 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8346044 [patent_doc_number] => 20120206964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-16 [patent_title] => 'PROGRAMMING RATE IDENTIFICATION AND CONTROL IN A SOLID STATE MEMORY' [patent_app_type] => utility [patent_app_number] => 13/454162 [patent_app_country] => US [patent_app_date] => 2012-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8993 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13454162 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8475825 [patent_doc_number] => 20120275232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-01 [patent_title] => 'SEMICONDUCTOR DEVICE AND ERASE METHODS THEREOF' [patent_app_type] => utility [patent_app_number] => 13/455016 [patent_app_country] => US [patent_app_date] => 2012-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 15033 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13455016 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8346053 [patent_doc_number] => 20120206974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-16 [patent_title] => 'SENSING FOR ALL BIT LINE ARCHITECTURE IN A MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/454381 [patent_app_country] => US [patent_app_date] => 2012-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3130 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13454381 [rel_patent_id] =>[rel_patent_doc_number] =>)