Search

Gene Nghia Auduong

Examiner (ID: 2491)

Most Active Art Unit
2827
Art Unit(s)
2827, 2712, 2818, 2825
Total Applications
1939
Issued Applications
1863
Pending Applications
12
Abandoned Applications
67

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16811785 [patent_doc_number] => 20210134340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => QUICK PRECHARGE FOR MEMORY SENSING [patent_app_type] => utility [patent_app_number] => 16/675065 [patent_app_country] => US [patent_app_date] => 2019-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18984 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16675065 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/675065
Quick precharge for memory sensing Nov 4, 2019 Issued
Array ( [id] => 15563799 [patent_doc_number] => 20200066311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => SEQUENTIAL MEMORY OPERATION WITHOUT DEACTIVATING ACCESS LINE SIGNALS [patent_app_type] => utility [patent_app_number] => 16/670480 [patent_app_country] => US [patent_app_date] => 2019-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10631 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16670480 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/670480
Sequential memory operation without deactivating access line signals Oct 30, 2019 Issued
Array ( [id] => 16193891 [patent_doc_number] => 20200234740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => STORAGE DEVICE AND OPERATING METHOD OF THE STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 16/670795 [patent_app_country] => US [patent_app_date] => 2019-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18412 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16670795 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/670795
Storage device and operating method of the storage device for controlling voltage rising time Oct 30, 2019 Issued
Array ( [id] => 17002370 [patent_doc_number] => 11081192 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => Memory plane structure for ultra-low read latency applications in non-volatile memories [patent_app_type] => utility [patent_app_number] => 16/668949 [patent_app_country] => US [patent_app_date] => 2019-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 9476 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16668949 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/668949
Memory plane structure for ultra-low read latency applications in non-volatile memories Oct 29, 2019 Issued
Array ( [id] => 16394222 [patent_doc_number] => 20200335163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-22 [patent_title] => NONVOLATILE MEMORY DEVICE INCLUDING BANKS OPERATING IN DIFFERENT OPERATION MODES, OPERATION METHOD OF MEMORY CONTROLLER, AND STORAGE DEVICE COMPRISING NONVOLATILE MEMORY DEVICE AND MEMORY CONTROLLER [patent_app_type] => utility [patent_app_number] => 16/654495 [patent_app_country] => US [patent_app_date] => 2019-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10587 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16654495 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/654495
Nonvolatile memory device including banks operating in different operation modes, operation method of memory controller, and storage device comprising nonvolatile memory device and memory controller Oct 15, 2019 Issued
Array ( [id] => 15461471 [patent_doc_number] => 20200043560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => SEMICONDUCTOR DEVICE AND OPERATING METHOD OF THE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/601240 [patent_app_country] => US [patent_app_date] => 2019-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5925 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16601240 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/601240
Semiconductor device including memory cells storing multi-bit data and operating method of the semiconductor device Oct 13, 2019 Issued
Array ( [id] => 15461467 [patent_doc_number] => 20200043558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => NONVOLATILE SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/597242 [patent_app_country] => US [patent_app_date] => 2019-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10788 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16597242 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/597242
Nonvolatile semiconductor memory device including a memory cell array and a control circuit applying a reading voltage Oct 8, 2019 Issued
Array ( [id] => 16668507 [patent_doc_number] => 10937765 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-02 [patent_title] => Semiconductor device with laminated semiconductor chips [patent_app_type] => utility [patent_app_number] => 16/595979 [patent_app_country] => US [patent_app_date] => 2019-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 8823 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16595979 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/595979
Semiconductor device with laminated semiconductor chips Oct 7, 2019 Issued
Array ( [id] => 16803115 [patent_doc_number] => 10998066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-04 [patent_title] => End of life performance throttling to prevent data loss [patent_app_type] => utility [patent_app_number] => 16/589956 [patent_app_country] => US [patent_app_date] => 2019-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10711 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16589956 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/589956
End of life performance throttling to prevent data loss Sep 30, 2019 Issued
Array ( [id] => 16364295 [patent_doc_number] => 20200321046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-08 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/578383 [patent_app_country] => US [patent_app_date] => 2019-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12832 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16578383 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/578383
Memory device Sep 21, 2019 Issued
Array ( [id] => 16943943 [patent_doc_number] => 11056191 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-06 [patent_title] => Nonvolatile memory device having different DQ lines receiving DQ line codes and method of operating nonvolatile memory device using different threshold voltages or error margins [patent_app_type] => utility [patent_app_number] => 16/571421 [patent_app_country] => US [patent_app_date] => 2019-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 27 [patent_no_of_words] => 12140 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16571421 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/571421
Nonvolatile memory device having different DQ lines receiving DQ line codes and method of operating nonvolatile memory device using different threshold voltages or error margins Sep 15, 2019 Issued
Array ( [id] => 16210139 [patent_doc_number] => 20200243129 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => ELECTRONIC CIRCUIT CAPABLE OF SELECTIVELY COMPENSATING FOR CROSSTALK NOISE AND INTER-SYMBOL INTERFERENCE [patent_app_type] => utility [patent_app_number] => 16/543765 [patent_app_country] => US [patent_app_date] => 2019-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11611 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16543765 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/543765
Electronic circuit capable of selectively compensating for crosstalk noise and inter-symbol interference Aug 18, 2019 Issued
Array ( [id] => 16249219 [patent_doc_number] => 10748591 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-18 [patent_title] => Random code generator [patent_app_type] => utility [patent_app_number] => 16/542671 [patent_app_country] => US [patent_app_date] => 2019-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5209 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16542671 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/542671
Random code generator Aug 15, 2019 Issued
Array ( [id] => 15217397 [patent_doc_number] => 20190371385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => APPARATUSES AND METHODS INCLUDING FERROELECTRIC MEMORY AND FOR ACCESSING FERROELECTRIC MEMORY [patent_app_type] => utility [patent_app_number] => 16/541614 [patent_app_country] => US [patent_app_date] => 2019-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7421 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16541614 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/541614
Apparatuses and methods including ferroelectric memory and for accessing ferroelectric memory Aug 14, 2019 Issued
Array ( [id] => 16356237 [patent_doc_number] => 10796754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-06 [patent_title] => Semiconductor storage device and memory system including semiconductor storage device and controller [patent_app_type] => utility [patent_app_number] => 16/536900 [patent_app_country] => US [patent_app_date] => 2019-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 54 [patent_no_of_words] => 36424 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16536900 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/536900
Semiconductor storage device and memory system including semiconductor storage device and controller Aug 8, 2019 Issued
Array ( [id] => 16132011 [patent_doc_number] => 10699772 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-30 [patent_title] => Utilization of instructions stored in an edge section of an array of memory cells [patent_app_type] => utility [patent_app_number] => 16/530244 [patent_app_country] => US [patent_app_date] => 2019-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 17267 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16530244 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/530244
Utilization of instructions stored in an edge section of an array of memory cells Aug 1, 2019 Issued
Array ( [id] => 16653145 [patent_doc_number] => 10930336 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-02-23 [patent_title] => Memory device and row-hammer refresh method thereof [patent_app_type] => utility [patent_app_number] => 16/528607 [patent_app_country] => US [patent_app_date] => 2019-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3529 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16528607 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/528607
Memory device and row-hammer refresh method thereof Jul 30, 2019 Issued
Array ( [id] => 16432653 [patent_doc_number] => 10832745 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-10 [patent_title] => Apparatuses and methods for performing operations using sense amplifiers and intermediary circuitry [patent_app_type] => utility [patent_app_number] => 16/523583 [patent_app_country] => US [patent_app_date] => 2019-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5685 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16523583 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/523583
Apparatuses and methods for performing operations using sense amplifiers and intermediary circuitry Jul 25, 2019 Issued
Array ( [id] => 15597159 [patent_doc_number] => 20200075114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => Data Storage Devices and Data Processing Methods [patent_app_type] => utility [patent_app_number] => 16/518615 [patent_app_country] => US [patent_app_date] => 2019-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8159 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16518615 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/518615
Data storage devices and data processing methods Jul 21, 2019 Issued
Array ( [id] => 15414399 [patent_doc_number] => 20200027522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-23 [patent_title] => MEMORY DEVICE AND MEMORY PERIPHERAL CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/516257 [patent_app_country] => US [patent_app_date] => 2019-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8276 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16516257 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/516257
Memory device and memory peripheral circuit Jul 18, 2019 Issued
Menu