Gene Nghia Auduong

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Array ( [id] => 9498316 [patent_doc_number] => 08737144 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-27 [patent_title] => 'Memory architecture and design methodology with adaptive read' [patent_app_type] => utility [patent_app_number] => 13/340670 [patent_app_country] => US [patent_app_date] => 2011-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9204 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13340670 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8852303 [patent_doc_number] => 20130141978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-06 [patent_title] => 'FLASH MEMORY DEVICES AND SYSTEMS' [patent_app_type] => utility [patent_app_number] => 13/340091 [patent_app_country] => US [patent_app_date] => 2011-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4319 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13340091 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8157080 [patent_doc_number] => 20120099376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-26 [patent_title] => 'THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY' [patent_app_type] => utility [patent_app_number] => 13/336122 [patent_app_country] => US [patent_app_date] => 2011-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 10398 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20120099376.pdf [firstpage_image] =>[orig_patent_app_number] => 13336122 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8125255 [patent_doc_number] => 20120087175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-12 [patent_title] => 'Asymmetric Write Current Compensation' [patent_app_type] => utility [patent_app_number] => 13/333598 [patent_app_country] => US [patent_app_date] => 2011-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6062 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20120087175.pdf [firstpage_image] =>[orig_patent_app_number] => 13333598 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8573205 [patent_doc_number] => 08339858 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-25 [patent_title] => 'Selecting programming voltages in response to at least a data latch in communication with a sense amplifier' [patent_app_type] => utility [patent_app_number] => 13/285697 [patent_app_country] => US [patent_app_date] => 2011-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 9238 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13285697 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7774876 [patent_doc_number] => 20120039128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-16 [patent_title] => 'THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY' [patent_app_type] => utility [patent_app_number] => 13/281591 [patent_app_country] => US [patent_app_date] => 2011-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9574 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20120039128.pdf [firstpage_image] =>[orig_patent_app_number] => 13281591 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13611307 [patent_doc_number] => 20180357203 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2018-12-13 [patent_title] => EFFICIENT AND SCALABLE MULTI-VALUE PROCESSOR AND SUPPORTING CIRCUITS [patent_app_type] => utility [patent_app_number] => 13/280662 [patent_app_country] => US [patent_app_date] => 2011-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6036 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13280662 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13611307 [patent_doc_number] => 20180357203 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2018-12-13 [patent_title] => EFFICIENT AND SCALABLE MULTI-VALUE PROCESSOR AND SUPPORTING CIRCUITS [patent_app_type] => utility [patent_app_number] => 13/280662 [patent_app_country] => US [patent_app_date] => 2011-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6036 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13280662 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7764841 [patent_doc_number] => 20120033497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-09 [patent_title] => 'NON-VOLATILE MEMORY DEVICE HAVING CONFIGURABLE PAGE SIZE' [patent_app_type] => utility [patent_app_number] => 13/276856 [patent_app_country] => US [patent_app_date] => 2011-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 14339 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20120033497.pdf [firstpage_image] =>[orig_patent_app_number] => 13276856 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8677003 [patent_doc_number] => 08385126 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-26 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 13/246004 [patent_app_country] => US [patent_app_date] => 2011-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 31 [patent_no_of_words] => 10779 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13246004 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9185412 [patent_doc_number] => 08625358 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-07 [patent_title] => 'Row driver circuit for NAND memories including a decoupling inverter' [patent_app_type] => utility [patent_app_number] => 13/245358 [patent_app_country] => US [patent_app_date] => 2011-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7844 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13245358 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8677010 [patent_doc_number] => 08385134 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-26 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 13/244448 [patent_app_country] => US [patent_app_date] => 2011-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 36 [patent_no_of_words] => 17568 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13244448 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8475836 [patent_doc_number] => 20120275243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-01 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/244363 [patent_app_country] => US [patent_app_date] => 2011-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2580 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13244363 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8157102 [patent_doc_number] => 20120099388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-26 [patent_title] => 'INTERNAL VOLTAGE GENERATOR OF SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/243490 [patent_app_country] => US [patent_app_date] => 2011-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4152 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20120099388.pdf [firstpage_image] =>[orig_patent_app_number] => 13243490 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8944991 [patent_doc_number] => 08498174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-30 [patent_title] => 'Dual-port subthreshold SRAM cell' [patent_app_type] => utility [patent_app_number] => 13/243690 [patent_app_country] => US [patent_app_date] => 2011-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2936 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13243690 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9185402 [patent_doc_number] => 08625348 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-07 [patent_title] => 'Nonvolatile memory devices and methods forming the same' [patent_app_type] => utility [patent_app_number] => 13/243968 [patent_app_country] => US [patent_app_date] => 2011-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 12755 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13243968 [rel_patent_id] =>[rel_patent_doc_number] =>)

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Array ( [id] => 8447727 [patent_doc_number] => 08289786 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-16 [patent_title] => 'Data storage using read-mask-write operation' [patent_app_type] => utility [patent_app_number] => 13/240359 [patent_app_country] => US [patent_app_date] => 2011-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3148 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13240359 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7746797 [patent_doc_number] => 20120023285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-26 [patent_title] => 'NON-VOLATILE MEMORY WITH DYNAMIC MULTI-MODE OPERATION' [patent_app_type] => utility [patent_app_number] => 13/239813 [patent_app_country] => US [patent_app_date] => 2011-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9326 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20120023285.pdf [firstpage_image] =>[orig_patent_app_number] => 13239813 [rel_patent_id] =>[rel_patent_doc_number] =>)