Gene Nghia Auduong

Array ( [id] => 5494544 [patent_doc_number] => 20090262572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-22 [patent_title] => 'MULTILAYER STORAGE CLASS MEMORY USING EXTERNALLY HEATED PHASE CHANGE MATERIAL' [patent_app_type] => utility [patent_app_number] => 12/107338 [patent_app_country] => US [patent_app_date] => 2008-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 7545 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20090262572.pdf [firstpage_image] =>[orig_patent_app_number] => 12107338 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4858101 [patent_doc_number] => 20080266951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'NON-VOLATILE MEMORY DEVICE AND PROGRAM METHOD' [patent_app_type] => utility [patent_app_number] => 12/106472 [patent_app_country] => US [patent_app_date] => 2008-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4397 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20080266951.pdf [firstpage_image] =>[orig_patent_app_number] => 12106472 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5451185 [patent_doc_number] => 20090067221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-12 [patent_title] => 'HIGH DENSITY 45NM SRAM USING SMALL-SIGNAL NON-STROBED REGENERATIVE SENSING' [patent_app_type] => utility [patent_app_number] => 12/105410 [patent_app_country] => US [patent_app_date] => 2008-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1568 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20090067221.pdf [firstpage_image] =>[orig_patent_app_number] => 12105410 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 179001 [patent_doc_number] => 07656712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-02 [patent_title] => 'Method and circuit for programming a memory cell, in particular of the NOR flash type' [patent_app_type] => utility [patent_app_number] => 12/104118 [patent_app_country] => US [patent_app_date] => 2008-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7385 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/656/07656712.pdf [firstpage_image] =>[orig_patent_app_number] => 12104118 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4811900 [patent_doc_number] => 20080192531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-14 [patent_title] => 'METHOD OF WRITING INTO SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/104018 [patent_app_country] => US [patent_app_date] => 2008-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10956 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0192/20080192531.pdf [firstpage_image] =>[orig_patent_app_number] => 12104018 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 315858 [patent_doc_number] => 07525836 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-28 [patent_title] => 'Non-imprinting memory with high speed erase' [patent_app_type] => utility [patent_app_number] => 12/103613 [patent_app_country] => US [patent_app_date] => 2008-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 6117 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/525/07525836.pdf [firstpage_image] =>[orig_patent_app_number] => 12103613 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 164687 [patent_doc_number] => 07672162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-02 [patent_title] => 'Non-volatile memory device, memory system, and LSB read method' [patent_app_type] => utility [patent_app_number] => 12/103176 [patent_app_country] => US [patent_app_date] => 2008-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5994 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/672/07672162.pdf [firstpage_image] =>[orig_patent_app_number] => 12103176 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 198892 [patent_doc_number] => 07639538 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-29 [patent_title] => 'Memory card, semiconductor device, and method of controlling memory card' [patent_app_type] => utility [patent_app_number] => 12/102649 [patent_app_country] => US [patent_app_date] => 2008-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 9980 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/639/07639538.pdf [firstpage_image] =>[orig_patent_app_number] => 12102649 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4958967 [patent_doc_number] => 20080273391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-06 [patent_title] => 'Regulator Bypass Start-Up in an Integrated Circuit Device' [patent_app_type] => utility [patent_app_number] => 12/102400 [patent_app_country] => US [patent_app_date] => 2008-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1859 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0273/20080273391.pdf [firstpage_image] =>[orig_patent_app_number] => 12102400 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 94710 [patent_doc_number] => 07738298 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-15 [patent_title] => 'Flash memory device' [patent_app_type] => utility [patent_app_number] => 12/102262 [patent_app_country] => US [patent_app_date] => 2008-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2895 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/738/07738298.pdf [firstpage_image] =>[orig_patent_app_number] => 12102262 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 26151 [patent_doc_number] => 07796417 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-09-14 [patent_title] => 'Memory circuits having programmable non-volatile resistors' [patent_app_type] => utility [patent_app_number] => 12/102736 [patent_app_country] => US [patent_app_date] => 2008-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 7519 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/796/07796417.pdf [firstpage_image] =>[orig_patent_app_number] => 12102736 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4674768 [patent_doc_number] => 20080212396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-04 [patent_title] => 'Delay Mechanism for Unbalanced Read/Write Paths in Domino SRAM Arrays' [patent_app_type] => utility [patent_app_number] => 12/098715 [patent_app_country] => US [patent_app_date] => 2008-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6022 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20080212396.pdf [firstpage_image] =>[orig_patent_app_number] => 12098715 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4858084 [patent_doc_number] => 20080266934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'NONVOLATILE MEMORY DEVICE AND METHOD TO CONTROL THE SAME' [patent_app_type] => utility [patent_app_number] => 12/060710 [patent_app_country] => US [patent_app_date] => 2008-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6013 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20080266934.pdf [firstpage_image] =>[orig_patent_app_number] => 12060710 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5269991 [patent_doc_number] => 20090073767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-19 [patent_title] => 'CONTROL GATE LINE ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 12/060746 [patent_app_country] => US [patent_app_date] => 2008-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 12984 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20090073767.pdf [firstpage_image] =>[orig_patent_app_number] => 12060746 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 315850 [patent_doc_number] => 07525828 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-28 [patent_title] => 'Semiconductor memory device and redundancy method thereof' [patent_app_type] => utility [patent_app_number] => 12/052020 [patent_app_country] => US [patent_app_date] => 2008-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7479 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/525/07525828.pdf [firstpage_image] =>[orig_patent_app_number] => 12052020 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 44978 [patent_doc_number] => 07782660 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-24 [patent_title] => 'Magnetically de-coupling magnetic memory cells and bit/word lines for reducing bit selection errors' [patent_app_type] => utility [patent_app_number] => 12/052326 [patent_app_country] => US [patent_app_date] => 2008-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 13 [patent_no_of_words] => 4033 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/782/07782660.pdf [firstpage_image] =>[orig_patent_app_number] => 12052326 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5402692 [patent_doc_number] => 20090238006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-24 [patent_title] => 'ADJUSTING PROGRAMMING OR ERASE VOLTAGE PULSES IN RESPONSE TO THE NUMBER OF PROGRAMMING OR ERASE FAILURES' [patent_app_type] => utility [patent_app_number] => 12/052228 [patent_app_country] => US [patent_app_date] => 2008-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8924 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0238/20090238006.pdf [firstpage_image] =>[orig_patent_app_number] => 12052228 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 192030 [patent_doc_number] => 07643349 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-05 [patent_title] => 'Efficient erase algorithm for SONOS-type NAND flash' [patent_app_type] => utility [patent_app_number] => 12/052276 [patent_app_country] => US [patent_app_date] => 2008-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 5890 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/643/07643349.pdf [firstpage_image] =>[orig_patent_app_number] => 12052276 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 144205 [patent_doc_number] => 07688640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-30 [patent_title] => 'Flash memory device and method for driving the same' [patent_app_type] => utility [patent_app_number] => 12/051930 [patent_app_country] => US [patent_app_date] => 2008-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 7281 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/688/07688640.pdf [firstpage_image] =>[orig_patent_app_number] => 12051930 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4750987 [patent_doc_number] => 20080159058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'WRITE LATENCY TRACKING USING A DELAY LOCK LOOP IN A SYNCHRONOUS DRAM' [patent_app_type] => utility [patent_app_number] => 12/047756 [patent_app_country] => US [patent_app_date] => 2008-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3153 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20080159058.pdf [firstpage_image] =>[orig_patent_app_number] => 12047756 [rel_patent_id] =>[rel_patent_doc_number] =>)