
Geoffrey L. Knable
Examiner (ID: 416, Phone: (571)272-1220 , Office: P/1747 )
| Most Active Art Unit | 1733 |
| Art Unit(s) | 1301, 3612, 1747, 1749, 1733, 1791, 1754 |
| Total Applications | 1885 |
| Issued Applications | 1261 |
| Pending Applications | 50 |
| Abandoned Applications | 575 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 142745
[patent_doc_number] => 07687938
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-03-30
[patent_title] => 'Superconducting shielding for use with an integrated circuit for quantum computing'
[patent_app_type] => utility
[patent_app_number] => 11/948817
[patent_app_country] => US
[patent_app_date] => 2007-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 7138
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/687/07687938.pdf
[firstpage_image] =>[orig_patent_app_number] => 11948817
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/948817 | Superconducting shielding for use with an integrated circuit for quantum computing | Nov 29, 2007 | Issued |
Array
(
[id] => 4431981
[patent_doc_number] => 07968466
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-06-28
[patent_title] => 'Fabrication process of a semiconductor device to form ultrafine patterns smaller than resolution limit of exposure apparatus'
[patent_app_type] => utility
[patent_app_number] => 11/945547
[patent_app_country] => US
[patent_app_date] => 2007-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 60
[patent_no_of_words] => 6271
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 217
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/968/07968466.pdf
[firstpage_image] =>[orig_patent_app_number] => 11945547
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/945547 | Fabrication process of a semiconductor device to form ultrafine patterns smaller than resolution limit of exposure apparatus | Nov 26, 2007 | Issued |
Array
(
[id] => 277938
[patent_doc_number] => 07557012
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-07-07
[patent_title] => 'Method for forming surface strap'
[patent_app_type] => utility
[patent_app_number] => 11/940308
[patent_app_country] => US
[patent_app_date] => 2007-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 2005
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/557/07557012.pdf
[firstpage_image] =>[orig_patent_app_number] => 11940308
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/940308 | Method for forming surface strap | Nov 13, 2007 | Issued |
Array
(
[id] => 5407366
[patent_doc_number] => 20090121264
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-05-14
[patent_title] => 'CMOS IMAGE SENSOR AND METHOD OF FORMING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/938757
[patent_app_country] => US
[patent_app_date] => 2007-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 5006
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0121/20090121264.pdf
[firstpage_image] =>[orig_patent_app_number] => 11938757
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/938757 | CMOS IMAGE SENSOR AND METHOD OF FORMING THE SAME | Nov 11, 2007 | Abandoned |
Array
(
[id] => 4782571
[patent_doc_number] => 20080135900
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-12
[patent_title] => 'METHOD OF FORMING ORGANIC FERROELECTRIC FILM, METHOD OF MANUFACTURING MEMORY ELEMENT, MEMORY DEVICE, AND ELECTRONIC APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 11/937197
[patent_app_country] => US
[patent_app_date] => 2007-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 11890
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0135/20080135900.pdf
[firstpage_image] =>[orig_patent_app_number] => 11937197
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/937197 | METHOD OF FORMING ORGANIC FERROELECTRIC FILM, METHOD OF MANUFACTURING MEMORY ELEMENT, MEMORY DEVICE, AND ELECTRONIC APPARATUS | Nov 7, 2007 | Abandoned |
Array
(
[id] => 5262366
[patent_doc_number] => 20090115051
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-05-07
[patent_title] => 'Electronic Circuit Package'
[patent_app_type] => utility
[patent_app_number] => 11/934007
[patent_app_country] => US
[patent_app_date] => 2007-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1655
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0115/20090115051.pdf
[firstpage_image] =>[orig_patent_app_number] => 11934007
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/934007 | Electronic Circuit Package | Oct 31, 2007 | Abandoned |
Array
(
[id] => 5327958
[patent_doc_number] => 20090108435
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-30
[patent_title] => 'ASSEMBLY INCLUDING PLURAL THROUGH WAFER VIAS, METHOD OF COOLING THE ASSEMBLY AND METHOD OF FABRICATING THE ASSEMBLY'
[patent_app_type] => utility
[patent_app_number] => 11/933107
[patent_app_country] => US
[patent_app_date] => 2007-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5059
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0108/20090108435.pdf
[firstpage_image] =>[orig_patent_app_number] => 11933107
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/933107 | Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly | Oct 30, 2007 | Issued |
Array
(
[id] => 4963164
[patent_doc_number] => 20080105984
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-08
[patent_title] => 'SEMICONDUCTOR CHIP STACK PACKAGE WITH REINFORCING MEMBER FOR PREVENTING PACKAGE WARPAGE CONNECTED TO SUBSTRATE'
[patent_app_type] => utility
[patent_app_number] => 11/933067
[patent_app_country] => US
[patent_app_date] => 2007-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 6467
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0105/20080105984.pdf
[firstpage_image] =>[orig_patent_app_number] => 11933067
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/933067 | SEMICONDUCTOR CHIP STACK PACKAGE WITH REINFORCING MEMBER FOR PREVENTING PACKAGE WARPAGE CONNECTED TO SUBSTRATE | Oct 30, 2007 | Abandoned |
Array
(
[id] => 5327973
[patent_doc_number] => 20090108450
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-30
[patent_title] => 'INTERCONNECT STRUCTURE AND METHOD OF MAKING SAME'
[patent_app_type] => utility
[patent_app_number] => 11/928327
[patent_app_country] => US
[patent_app_date] => 2007-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2390
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0108/20090108450.pdf
[firstpage_image] =>[orig_patent_app_number] => 11928327
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/928327 | INTERCONNECT STRUCTURE AND METHOD OF MAKING SAME | Oct 29, 2007 | Abandoned |
Array
(
[id] => 4890812
[patent_doc_number] => 20080099909
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-01
[patent_title] => 'WAFER STACKED PACKAGE HAVING VERTICAL HEAT EMISSION PATH AND METHOD OF FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/927457
[patent_app_country] => US
[patent_app_date] => 2007-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 5711
[patent_no_of_claims] => 42
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0099/20080099909.pdf
[firstpage_image] =>[orig_patent_app_number] => 11927457
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/927457 | Wafer stacked package having vertical heat emission path and method of fabricating the same | Oct 28, 2007 | Issued |
Array
(
[id] => 4487228
[patent_doc_number] => 07902577
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-03-08
[patent_title] => 'Image sensor having heterojunction bipolar transistor and method of fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/872308
[patent_app_country] => US
[patent_app_date] => 2007-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 22
[patent_no_of_words] => 4825
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 237
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/902/07902577.pdf
[firstpage_image] =>[orig_patent_app_number] => 11872308
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/872308 | Image sensor having heterojunction bipolar transistor and method of fabricating the same | Oct 14, 2007 | Issued |
Array
(
[id] => 190832
[patent_doc_number] => 07642143
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-01-05
[patent_title] => 'Method of fabricating thin film transistor having multilayer structure and active matrix display device including the thin film transistor'
[patent_app_type] => utility
[patent_app_number] => 11/870809
[patent_app_country] => US
[patent_app_date] => 2007-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 15
[patent_no_of_words] => 3256
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/642/07642143.pdf
[firstpage_image] =>[orig_patent_app_number] => 11870809
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/870809 | Method of fabricating thin film transistor having multilayer structure and active matrix display device including the thin film transistor | Oct 10, 2007 | Issued |
Array
(
[id] => 4825894
[patent_doc_number] => 20080124849
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-29
[patent_title] => 'FABRICATING METHOD OF SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/869518
[patent_app_country] => US
[patent_app_date] => 2007-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1527
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0124/20080124849.pdf
[firstpage_image] =>[orig_patent_app_number] => 11869518
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/869518 | FABRICATING METHOD OF SEMICONDUCTOR DEVICE | Oct 8, 2007 | Abandoned |
Array
(
[id] => 4749068
[patent_doc_number] => 20080157139
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-03
[patent_title] => 'IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/869479
[patent_app_country] => US
[patent_app_date] => 2007-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2303
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0157/20080157139.pdf
[firstpage_image] =>[orig_patent_app_number] => 11869479
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/869479 | IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME | Oct 8, 2007 | Abandoned |
Array
(
[id] => 4941817
[patent_doc_number] => 20080079140
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-03
[patent_title] => 'ELECTRONIC SYSTEM MODULES AND METHOD OF FABRICATON'
[patent_app_type] => utility
[patent_app_number] => 11/868919
[patent_app_country] => US
[patent_app_date] => 2007-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 12334
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 19
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0079/20080079140.pdf
[firstpage_image] =>[orig_patent_app_number] => 11868919
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/868919 | ELECTRONIC SYSTEM MODULES AND METHOD OF FABRICATON | Oct 7, 2007 | Abandoned |
Array
(
[id] => 211828
[patent_doc_number] => 07622734
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-11-24
[patent_title] => 'Organic transistor using self-assembled monolayer'
[patent_app_type] => utility
[patent_app_number] => 11/865769
[patent_app_country] => US
[patent_app_date] => 2007-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 6254
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/622/07622734.pdf
[firstpage_image] =>[orig_patent_app_number] => 11865769
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/865769 | Organic transistor using self-assembled monolayer | Oct 1, 2007 | Issued |
Array
(
[id] => 5425793
[patent_doc_number] => 20090085103
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-02
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD'
[patent_app_type] => utility
[patent_app_number] => 11/864238
[patent_app_country] => US
[patent_app_date] => 2007-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5341
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0085/20090085103.pdf
[firstpage_image] =>[orig_patent_app_number] => 11864238
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/864238 | Semiconductor device including a free wheeling diode | Sep 27, 2007 | Issued |
Array
(
[id] => 5505850
[patent_doc_number] => 20090079057
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-03-26
[patent_title] => 'INTEGRATED CIRCUIT DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/859898
[patent_app_country] => US
[patent_app_date] => 2007-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2260
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0079/20090079057.pdf
[firstpage_image] =>[orig_patent_app_number] => 11859898
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/859898 | INTEGRATED CIRCUIT DEVICE | Sep 23, 2007 | Abandoned |
Array
(
[id] => 4619621
[patent_doc_number] => 07999342
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-08-16
[patent_title] => 'Image sensor element for backside-illuminated sensor'
[patent_app_type] => utility
[patent_app_number] => 11/859848
[patent_app_country] => US
[patent_app_date] => 2007-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6162
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/999/07999342.pdf
[firstpage_image] =>[orig_patent_app_number] => 11859848
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/859848 | Image sensor element for backside-illuminated sensor | Sep 23, 2007 | Issued |
Array
(
[id] => 72597
[patent_doc_number] => 07755089
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-07-13
[patent_title] => 'Semiconductor device including complementary MOS transistor having a strained Si channel'
[patent_app_type] => utility
[patent_app_number] => 11/858408
[patent_app_country] => US
[patent_app_date] => 2007-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 33
[patent_no_of_words] => 5716
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 224
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/755/07755089.pdf
[firstpage_image] =>[orig_patent_app_number] => 11858408
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/858408 | Semiconductor device including complementary MOS transistor having a strained Si channel | Sep 19, 2007 | Issued |