Search

Geoffrey L. Knable

Examiner (ID: 416, Phone: (571)272-1220 , Office: P/1747 )

Most Active Art Unit
1733
Art Unit(s)
1301, 3612, 1747, 1749, 1733, 1791, 1754
Total Applications
1885
Issued Applications
1261
Pending Applications
50
Abandoned Applications
575

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8375783 [patent_doc_number] => 08258575 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-04 [patent_title] => 'Isolated drain-centric lateral MOSFET' [patent_app_type] => utility [patent_app_number] => 12/807675 [patent_app_country] => US [patent_app_date] => 2010-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 49 [patent_no_of_words] => 23846 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12807675 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/807675
Isolated drain-centric lateral MOSFET Sep 9, 2010 Issued
Array ( [id] => 8720748 [patent_doc_number] => 20130071965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-21 [patent_title] => 'In-Situ Fabrication Method for Silicon Solar Cell' [patent_app_type] => utility [patent_app_number] => 13/699739 [patent_app_country] => US [patent_app_date] => 2010-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5336 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13699739 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/699739
In-situ fabrication method for silicon solar cell Sep 7, 2010 Issued
Array ( [id] => 8630460 [patent_doc_number] => 08362533 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-29 [patent_title] => 'Semiconductor device including a transistor and a ferroelectric capacitor' [patent_app_type] => utility [patent_app_number] => 12/869502 [patent_app_country] => US [patent_app_date] => 2010-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 19329 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12869502 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/869502
Semiconductor device including a transistor and a ferroelectric capacitor Aug 25, 2010 Issued
Array ( [id] => 6021291 [patent_doc_number] => 20110049617 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/868048 [patent_app_country] => US [patent_app_date] => 2010-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 42 [patent_no_of_words] => 13470 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20110049617.pdf [firstpage_image] =>[orig_patent_app_number] => 12868048 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/868048
SEMICONDUCTOR DEVICE Aug 24, 2010 Abandoned
Array ( [id] => 6569422 [patent_doc_number] => 20100320432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-23 [patent_title] => 'VERTICAL MOSFET TRANSISTOR, IN PARTICULAR OPERATING AS A SELECTOR IN NONVOLATILE MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 12/862624 [patent_app_country] => US [patent_app_date] => 2010-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4543 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0320/20100320432.pdf [firstpage_image] =>[orig_patent_app_number] => 12862624 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/862624
Vertical mosfet transistor, in particular operating as a selector in nonvolatile memory devices Aug 23, 2010 Issued
Array ( [id] => 6511982 [patent_doc_number] => 20100261296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-14 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/821080 [patent_app_country] => US [patent_app_date] => 2010-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8894 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0261/20100261296.pdf [firstpage_image] =>[orig_patent_app_number] => 12821080 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/821080
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Jun 21, 2010 Abandoned
Array ( [id] => 6507071 [patent_doc_number] => 20100219426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-02 [patent_title] => 'LIGHT EMITTING DEVICE HAVING VERTICALLY STACKED LIGHT EMITTING DIODES' [patent_app_type] => utility [patent_app_number] => 12/775008 [patent_app_country] => US [patent_app_date] => 2010-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9330 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20100219426.pdf [firstpage_image] =>[orig_patent_app_number] => 12775008 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/775008
Light emitting device having vertically stacked light emitting diodes May 5, 2010 Issued
Array ( [id] => 7720391 [patent_doc_number] => 20120009726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-12 [patent_title] => 'METHOD FOR MANUFACTURING A SOLAR CELL MODULE PROVIDED WITH AN EDGE SPACE' [patent_app_type] => utility [patent_app_number] => 13/259539 [patent_app_country] => US [patent_app_date] => 2010-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4419 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20120009726.pdf [firstpage_image] =>[orig_patent_app_number] => 13259539 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/259539
Method for manufacturing a solar cell module provided with an edge space Apr 15, 2010 Issued
Array ( [id] => 6540695 [patent_doc_number] => 20100221897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-02 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/727521 [patent_app_country] => US [patent_app_date] => 2010-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 27940 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20100221897.pdf [firstpage_image] =>[orig_patent_app_number] => 12727521 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/727521
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME Mar 18, 2010 Abandoned
Array ( [id] => 6419093 [patent_doc_number] => 20100167487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'MASK ROM DEVICES AND METHODS FOR FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/723265 [patent_app_country] => US [patent_app_date] => 2010-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8194 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20100167487.pdf [firstpage_image] =>[orig_patent_app_number] => 12723265 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/723265
MASK ROM DEVICES AND METHODS FOR FORMING THE SAME Mar 11, 2010 Abandoned
Array ( [id] => 6393374 [patent_doc_number] => 20100164087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'Semiconductor device having a stacked chip structure' [patent_app_type] => utility [patent_app_number] => 12/659296 [patent_app_country] => US [patent_app_date] => 2010-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3497 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20100164087.pdf [firstpage_image] =>[orig_patent_app_number] => 12659296 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/659296
Semiconductor device having a stacked chip structure Mar 2, 2010 Abandoned
Array ( [id] => 9227402 [patent_doc_number] => 08633070 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-21 [patent_title] => 'Lightly doped source/drain last method for dual-epi integration' [patent_app_type] => utility [patent_app_number] => 12/716100 [patent_app_country] => US [patent_app_date] => 2010-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4937 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12716100 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/716100
Lightly doped source/drain last method for dual-epi integration Mar 1, 2010 Issued
Array ( [id] => 6614779 [patent_doc_number] => 20100224985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-09 [patent_title] => 'Chip-Scale Packaging with Protective Heat Spreader' [patent_app_type] => utility [patent_app_number] => 12/716197 [patent_app_country] => US [patent_app_date] => 2010-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9841 [patent_no_of_claims] => 85 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20100224985.pdf [firstpage_image] =>[orig_patent_app_number] => 12716197 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/716197
Chip-scale packaging with protective heat spreader Mar 1, 2010 Issued
Array ( [id] => 6613409 [patent_doc_number] => 20100224897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-09 [patent_title] => 'SEMICONDUCTOR OPTOELECTRONIC DEVICE AND METHOD FOR FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/716040 [patent_app_country] => US [patent_app_date] => 2010-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7512 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20100224897.pdf [firstpage_image] =>[orig_patent_app_number] => 12716040 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/716040
SEMICONDUCTOR OPTOELECTRONIC DEVICE AND METHOD FOR FORMING THE SAME Mar 1, 2010 Abandoned
Array ( [id] => 8352470 [patent_doc_number] => 08247799 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-21 [patent_title] => 'Superconducting shielding for use with an integrated circuit for quantum computing' [patent_app_type] => utility [patent_app_number] => 12/703534 [patent_app_country] => US [patent_app_date] => 2010-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7158 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12703534 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/703534
Superconducting shielding for use with an integrated circuit for quantum computing Feb 9, 2010 Issued
Array ( [id] => 6462368 [patent_doc_number] => 20100090751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-15 [patent_title] => 'Electrical Fuse Structure and Method' [patent_app_type] => utility [patent_app_number] => 12/637510 [patent_app_country] => US [patent_app_date] => 2009-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5583 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20100090751.pdf [firstpage_image] =>[orig_patent_app_number] => 12637510 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/637510
Electrical Fuse Structure and Method Dec 13, 2009 Abandoned
Array ( [id] => 6545843 [patent_doc_number] => 20100044855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-25 [patent_title] => 'INTEGRATED THERMAL STRUCTURES AND FABRICATION METHODS THEREOF FACILITATING IMPLEMENTING A CELL PHONE OR OTHER ELECTRONIC SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/611405 [patent_app_country] => US [patent_app_date] => 2009-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 16533 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20100044855.pdf [firstpage_image] =>[orig_patent_app_number] => 12611405 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/611405
Integrated thermal structures and fabrication methods thereof facilitating implementing a cell phone or other electronic system Nov 2, 2009 Issued
Array ( [id] => 7801575 [patent_doc_number] => 08129849 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-03-06 [patent_title] => 'Method of making semiconductor package with adhering portion' [patent_app_type] => utility [patent_app_number] => 12/589868 [patent_app_country] => US [patent_app_date] => 2009-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 9756 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/129/08129849.pdf [firstpage_image] =>[orig_patent_app_number] => 12589868 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/589868
Method of making semiconductor package with adhering portion Oct 27, 2009 Issued
Array ( [id] => 6448109 [patent_doc_number] => 20100038769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-18 [patent_title] => 'WAFER STACKED PACKAGE WAVING BERTICAL HEAT EMISSION PATH AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/581920 [patent_app_country] => US [patent_app_date] => 2009-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5724 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20100038769.pdf [firstpage_image] =>[orig_patent_app_number] => 12581920 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/581920
Wafer stacked package waving bertical heat emission path and method of fabricating the same Oct 19, 2009 Issued
Array ( [id] => 6036521 [patent_doc_number] => 20110089570 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-21 [patent_title] => 'Multi-Layer Connection Cell' [patent_app_type] => utility [patent_app_number] => 12/582635 [patent_app_country] => US [patent_app_date] => 2009-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2571 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20110089570.pdf [firstpage_image] =>[orig_patent_app_number] => 12582635 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/582635
Multi-Layer Connection Cell Oct 19, 2009 Abandoned
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