Search

Geoffrey S. Evans

Examiner (ID: 10565, Phone: (571)272-1174 , Office: P/3742 )

Most Active Art Unit
1725
Art Unit(s)
3742, 1742, 1725, 2831, 2104, 2106, 3761, 1793, 2103
Total Applications
3744
Issued Applications
3191
Pending Applications
123
Abandoned Applications
441

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18494224 [patent_doc_number] => 11699645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-11 [patent_title] => Semiconductor device having wiring substrate with lead-out wirings [patent_app_type] => utility [patent_app_number] => 17/529972 [patent_app_country] => US [patent_app_date] => 2021-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 9804 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 405 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17529972 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/529972
Semiconductor device having wiring substrate with lead-out wirings Nov 17, 2021 Issued
Array ( [id] => 19029949 [patent_doc_number] => 11929315 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-12 [patent_title] => Semiconductor package having pad with regular and irregular depressions and protrusions and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/527414 [patent_app_country] => US [patent_app_date] => 2021-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 7829 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17527414 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/527414
Semiconductor package having pad with regular and irregular depressions and protrusions and method of manufacturing the same Nov 15, 2021 Issued
Array ( [id] => 18796966 [patent_doc_number] => 11830801 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Chip-on-film package and semiconductor chip each having a readout circuit for a touch driving signal and a source channel circuit for outputting a pixel driving signal [patent_app_type] => utility [patent_app_number] => 17/527119 [patent_app_country] => US [patent_app_date] => 2021-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3181 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17527119 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/527119
Chip-on-film package and semiconductor chip each having a readout circuit for a touch driving signal and a source channel circuit for outputting a pixel driving signal Nov 14, 2021 Issued
Array ( [id] => 17885214 [patent_doc_number] => 20220300691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => INTEGRATED CIRCUIT HAVING EACH STANDARD CELL WITH SAME TARGET PITCH AND LAYOUT METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/453893 [patent_app_country] => US [patent_app_date] => 2021-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5604 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17453893 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/453893
Integrated circuit having each standard cell with same target pitch and layout method thereof Nov 7, 2021 Issued
Array ( [id] => 18365746 [patent_doc_number] => 20230147337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => THREE-DIMENSIONAL LTCC PACKAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/520665 [patent_app_country] => US [patent_app_date] => 2021-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3856 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17520665 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/520665
THREE-DIMENSIONAL LTCC PACKAGE STRUCTURE Nov 5, 2021 Abandoned
Array ( [id] => 18339709 [patent_doc_number] => 20230131658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => THREE-DIMENSIONAL LTCC PACKAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/512564 [patent_app_country] => US [patent_app_date] => 2021-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3567 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17512564 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/512564
THREE-DIMENSIONAL LTCC PACKAGE STRUCTURE Oct 26, 2021 Abandoned
Array ( [id] => 18335008 [patent_doc_number] => 20230126956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => METHOD FOR MANUFACTURING A THREE-DIMENSIONAL LTCC PACKAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/512600 [patent_app_country] => US [patent_app_date] => 2021-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3602 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17512600 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/512600
METHOD FOR MANUFACTURING A THREE-DIMENSIONAL LTCC PACKAGE STRUCTURE Oct 26, 2021 Abandoned
Array ( [id] => 17566597 [patent_doc_number] => 20220130746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/508944 [patent_app_country] => US [patent_app_date] => 2021-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14014 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17508944 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/508944
Wiring substrate and semiconductor device each having first and second via wirings Oct 21, 2021 Issued
Array ( [id] => 20111533 [patent_doc_number] => 12362269 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Integrated circuit (IC) packages employing supplemental metal layer coupled to embedded metal traces in a die-side embedded trace substrate (ETS) layer, and related fabrication methods [patent_app_type] => utility [patent_app_number] => 17/451302 [patent_app_country] => US [patent_app_date] => 2021-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 27 [patent_no_of_words] => 10578 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17451302 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/451302
Integrated circuit (IC) packages employing supplemental metal layer coupled to embedded metal traces in a die-side embedded trace substrate (ETS) layer, and related fabrication methods Oct 17, 2021 Issued
Array ( [id] => 19796286 [patent_doc_number] => 12237255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-25 [patent_title] => Vertical interconnects with variable pitch for scalable escape routing [patent_app_type] => utility [patent_app_number] => 17/499712 [patent_app_country] => US [patent_app_date] => 2021-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 10630 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17499712 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/499712
Vertical interconnects with variable pitch for scalable escape routing Oct 11, 2021 Issued
Array ( [id] => 17536704 [patent_doc_number] => 20220115313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => Low RF crosstalk devices via a slot for isolation [patent_app_type] => utility [patent_app_number] => 17/494106 [patent_app_country] => US [patent_app_date] => 2021-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2782 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17494106 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/494106
Low RF crosstalk devices via a slot for isolation Oct 4, 2021 Issued
Array ( [id] => 18281764 [patent_doc_number] => 20230097236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => SUBSTRATE LAYER COUNT REDUCTION ENABLED WITH BUMP PITCH SCALE THROUGH GLASS CORE VIA PITCH [patent_app_type] => utility [patent_app_number] => 17/485287 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7550 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485287 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/485287
SUBSTRATE LAYER COUNT REDUCTION ENABLED WITH BUMP PITCH SCALE THROUGH GLASS CORE VIA PITCH Sep 23, 2021 Abandoned
Array ( [id] => 18264852 [patent_doc_number] => 20230086094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => INTEGRATED CIRCUIT (IC) PACKAGE EMPLOYING ADDED METAL FOR EMBEDDED METAL TRACES IN ETS-BASED SUBSTRATE FOR REDUCED SIGNAL PATH IMPEDANCE, AND RELATED FABRICATION METHODS [patent_app_type] => utility [patent_app_number] => 17/482718 [patent_app_country] => US [patent_app_date] => 2021-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15029 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17482718 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/482718
Integrated circuit (IC) package employing added metal for embedded metal traces in ETS-based substrate for reduced signal path impedance, and related fabrication methods Sep 22, 2021 Issued
Array ( [id] => 19371679 [patent_doc_number] => 12063784 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-13 [patent_title] => Memory peripheral circuit having three-dimensional transistors and method for forming the same [patent_app_type] => utility [patent_app_number] => 17/482046 [patent_app_country] => US [patent_app_date] => 2021-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 53 [patent_no_of_words] => 26927 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17482046 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/482046
Memory peripheral circuit having three-dimensional transistors and method for forming the same Sep 21, 2021 Issued
Array ( [id] => 19416546 [patent_doc_number] => 12082408 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Three-dimensional memory devices having first semiconductor structure bonded with second semiconductor structure each including peripheral circuit and methods for forming the same [patent_app_type] => utility [patent_app_number] => 17/481803 [patent_app_country] => US [patent_app_date] => 2021-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 73 [patent_figures_cnt] => 100 [patent_no_of_words] => 54976 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17481803 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/481803
Three-dimensional memory devices having first semiconductor structure bonded with second semiconductor structure each including peripheral circuit and methods for forming the same Sep 21, 2021 Issued
Array ( [id] => 18891056 [patent_doc_number] => 11869833 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-09 [patent_title] => Package comprising a substrate with a via interconnect coupled to a trace interconnect and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 17/476383 [patent_app_country] => US [patent_app_date] => 2021-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 12488 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17476383 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/476383
Package comprising a substrate with a via interconnect coupled to a trace interconnect and method of fabricating the same Sep 14, 2021 Issued
Array ( [id] => 20361760 [patent_doc_number] => 12477778 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => Epitaxial structure for source/drain contact for semiconductor structure having fin structure [patent_app_type] => utility [patent_app_number] => 17/472540 [patent_app_country] => US [patent_app_date] => 2021-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 34 [patent_no_of_words] => 4267 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17472540 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/472540
Epitaxial structure for source/drain contact for semiconductor structure having fin structure Sep 9, 2021 Issued
Array ( [id] => 18600243 [patent_doc_number] => 20230275044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => ELECTRONIC COMPONENT PACKAGE WITH INTEGRATED COMPONENT AND REDISTRIBUTION LAYER STACK [patent_app_type] => utility [patent_app_number] => 18/040170 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5470 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18040170 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/040170
ELECTRONIC COMPONENT PACKAGE WITH INTEGRATED COMPONENT AND REDISTRIBUTION LAYER STACK Sep 6, 2021 Abandoned
Array ( [id] => 17302977 [patent_doc_number] => 20210398816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-23 [patent_title] => INVERSE TONE PILLAR PRINTING [patent_app_type] => utility [patent_app_number] => 17/467428 [patent_app_country] => US [patent_app_date] => 2021-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7303 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17467428 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/467428
Inverse tone pillar printing method using organic planarizing layer pillars Sep 5, 2021 Issued
Array ( [id] => 18224310 [patent_doc_number] => 20230063304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => HYBRID ORGANIC AND NON-ORGANIC INTERPOSER WITH EMBEDDED COMPONENT AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/462057 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15634 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17462057 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/462057
Semiconductor device having an integrated device positioned within a hybrid interposer that includes organic and non-organic materials Aug 30, 2021 Issued
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