Search

Geoffrey S. Evans

Examiner (ID: 10565, Phone: (571)272-1174 , Office: P/3742 )

Most Active Art Unit
1725
Art Unit(s)
3742, 1742, 1725, 2831, 2104, 2106, 3761, 1793, 2103
Total Applications
3744
Issued Applications
3191
Pending Applications
123
Abandoned Applications
441

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18736915 [patent_doc_number] => 11805671 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-31 [patent_title] => Method for manufacturing display backplane, display backplane, and display device [patent_app_type] => utility [patent_app_number] => 17/356380 [patent_app_country] => US [patent_app_date] => 2021-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4528 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17356380 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/356380
Method for manufacturing display backplane, display backplane, and display device Jun 22, 2021 Issued
Array ( [id] => 17486181 [patent_doc_number] => 20220093685 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/346478 [patent_app_country] => US [patent_app_date] => 2021-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10405 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17346478 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/346478
Semiconductor memory device having memory layer extending between insulation layer and semiconductor layer Jun 13, 2021 Issued
Array ( [id] => 19330439 [patent_doc_number] => 12048139 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Manufacturing method of semiconductor structure using first mask layer and first photoresist layer to selectively etch stack on complete die region [patent_app_type] => utility [patent_app_number] => 17/438436 [patent_app_country] => US [patent_app_date] => 2021-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 5241 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17438436 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/438436
Manufacturing method of semiconductor structure using first mask layer and first photoresist layer to selectively etch stack on complete die region Jun 10, 2021 Issued
Array ( [id] => 17303054 [patent_doc_number] => 20210398893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-23 [patent_title] => QUANTUM DEVICE [patent_app_type] => utility [patent_app_number] => 17/345426 [patent_app_country] => US [patent_app_date] => 2021-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13192 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17345426 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/345426
Quantum device having quantum chip on interposer in contact with sample stage Jun 10, 2021 Issued
Array ( [id] => 20776758 [patent_doc_number] => 12660453 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-16 [patent_title] => Display substrate and display apparatus each having first power supply pins connected with first power supply line [patent_app_type] => utility [patent_app_number] => 17/780033 [patent_app_country] => US [patent_app_date] => 2021-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 25 [patent_no_of_words] => 9680 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 399 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17780033 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/780033
Display substrate and display apparatus each having first power supply pins connected with first power supply line Jun 3, 2021 Issued
Array ( [id] => 18766941 [patent_doc_number] => 11817350 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Method for manufacturing standard cell regions and engineering change order (ECO) cell regions [patent_app_type] => utility [patent_app_number] => 17/332819 [patent_app_country] => US [patent_app_date] => 2021-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 38 [patent_no_of_words] => 14490 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17332819 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/332819
Method for manufacturing standard cell regions and engineering change order (ECO) cell regions May 26, 2021 Issued
Array ( [id] => 19926457 [patent_doc_number] => 12300753 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Thin film transistor and array substrate each having active layer comprising multiple oxide layers arranged in a stack [patent_app_type] => utility [patent_app_number] => 17/780877 [patent_app_country] => US [patent_app_date] => 2021-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 39 [patent_no_of_words] => 18197 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17780877 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/780877
Thin film transistor and array substrate each having active layer comprising multiple oxide layers arranged in a stack May 26, 2021 Issued
Array ( [id] => 18999298 [patent_doc_number] => 11916155 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Optoelectronic package having second encapsulant cover first encapsulant and photonic devices [patent_app_type] => utility [patent_app_number] => 17/326356 [patent_app_country] => US [patent_app_date] => 2021-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 6616 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17326356 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/326356
Optoelectronic package having second encapsulant cover first encapsulant and photonic devices May 20, 2021 Issued
Array ( [id] => 17085688 [patent_doc_number] => 20210280695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => Semiconductor Structure Cutting Process and Structures Formed Thereby [patent_app_type] => utility [patent_app_number] => 17/325622 [patent_app_country] => US [patent_app_date] => 2021-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10249 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17325622 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/325622
Semiconductor structure having dielectric structure extending into second cavity of semiconductor Fin May 19, 2021 Issued
Array ( [id] => 19079625 [patent_doc_number] => 11949006 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Power semiconductor device with p-contact and doped insulation blocks defining contact holes [patent_app_type] => utility [patent_app_number] => 17/325710 [patent_app_country] => US [patent_app_date] => 2021-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 14478 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17325710 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/325710
Power semiconductor device with p-contact and doped insulation blocks defining contact holes May 19, 2021 Issued
Array ( [id] => 17509310 [patent_doc_number] => 20220102413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => IMAGE SENSING DEVICE [patent_app_type] => utility [patent_app_number] => 17/319767 [patent_app_country] => US [patent_app_date] => 2021-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12462 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17319767 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/319767
Image sensing device having lens with plurality of portions each corresponding to at least one of plurality of phase-difference detection pixels May 12, 2021 Issued
Array ( [id] => 19183797 [patent_doc_number] => 11990398 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-21 [patent_title] => Semiconductor package device having chip substrate with pads around photosensitive region [patent_app_type] => utility [patent_app_number] => 17/317062 [patent_app_country] => US [patent_app_date] => 2021-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 5534 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17317062 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/317062
Semiconductor package device having chip substrate with pads around photosensitive region May 10, 2021 Issued
Array ( [id] => 17993326 [patent_doc_number] => 20220359363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/315067 [patent_app_country] => US [patent_app_date] => 2021-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7181 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17315067 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/315067
Semiconductor package structure having substrate with embedded electronic component and conductive pillars May 6, 2021 Issued
Array ( [id] => 17523116 [patent_doc_number] => 20220108965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-07 [patent_title] => LOW TEMPERATURE, REWORKABLE, AND NO-UNDERFILL ATTACH PROCESS FOR FINE PITCH BALL GRID ARRAYS HAVING SOLDER BALLS WITH EPOXY AND SOLDER MATERIAL [patent_app_type] => utility [patent_app_number] => 17/314356 [patent_app_country] => US [patent_app_date] => 2021-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2277 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17314356 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/314356
LOW TEMPERATURE, REWORKABLE, AND NO-UNDERFILL ATTACH PROCESS FOR FINE PITCH BALL GRID ARRAYS HAVING SOLDER BALLS WITH EPOXY AND SOLDER MATERIAL May 6, 2021 Abandoned
Array ( [id] => 17056169 [patent_doc_number] => 20210265603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => METHODS FOR HMDSO THERMAL STABILITY [patent_app_type] => utility [patent_app_number] => 17/313867 [patent_app_country] => US [patent_app_date] => 2021-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3869 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17313867 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/313867
Methods for HMDSO thermal stability May 5, 2021 Issued
Array ( [id] => 17040815 [patent_doc_number] => 20210257451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-19 [patent_title] => VERTICAL 2D STRUCTURES FOR ADVANCED ELECTRONIC AND OPTOELECTRONIC SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/246997 [patent_app_country] => US [patent_app_date] => 2021-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9878 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17246997 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/246997
Method of fabricating vertically oriented planar structures for advanced electronic and optoelectronic systems May 2, 2021 Issued
Array ( [id] => 19567801 [patent_doc_number] => 12142580 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-12 [patent_title] => Integrated circuit physical security device having a security cover for an integrated circuit [patent_app_type] => utility [patent_app_number] => 17/306034 [patent_app_country] => US [patent_app_date] => 2021-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 52 [patent_no_of_words] => 42564 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17306034 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/306034
Integrated circuit physical security device having a security cover for an integrated circuit May 2, 2021 Issued
Array ( [id] => 17986065 [patent_doc_number] => 20220352102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/244971 [patent_app_country] => US [patent_app_date] => 2021-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4711 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17244971 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/244971
SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME Apr 29, 2021 Abandoned
Array ( [id] => 17582870 [patent_doc_number] => 20220139725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => Semiconductor Devices and Methods of Manufacture [patent_app_type] => utility [patent_app_number] => 17/245856 [patent_app_country] => US [patent_app_date] => 2021-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11620 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17245856 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/245856
Methods of manufacture of semiconductor devices having redistribution layer using dielectric material having photoactive component Apr 29, 2021 Issued
Array ( [id] => 19783344 [patent_doc_number] => 12232399 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Display substrate, display panel, and method of manufacturing display substrate having scan driving circuit in non-light-emitting region of pixel units [patent_app_type] => utility [patent_app_number] => 17/754000 [patent_app_country] => US [patent_app_date] => 2021-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 13436 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17754000 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/754000
Display substrate, display panel, and method of manufacturing display substrate having scan driving circuit in non-light-emitting region of pixel units Apr 27, 2021 Issued
Menu