Search

George A. Bugg

Supervisory Patent Examiner (ID: 17783, Phone: (571)272-2998 , Office: P/2682 )

Most Active Art Unit
2612
Art Unit(s)
2911, 2682, 2612, 2636, 2613
Total Applications
454
Issued Applications
269
Pending Applications
78
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16760106 [patent_doc_number] => 10978664 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-13 [patent_title] => Display substrate and method for manufacturing the same and display device [patent_app_type] => utility [patent_app_number] => 16/409369 [patent_app_country] => US [patent_app_date] => 2019-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4152 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16409369 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/409369
Display substrate and method for manufacturing the same and display device May 9, 2019 Issued
Array ( [id] => 16760106 [patent_doc_number] => 10978664 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-13 [patent_title] => Display substrate and method for manufacturing the same and display device [patent_app_type] => utility [patent_app_number] => 16/409369 [patent_app_country] => US [patent_app_date] => 2019-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4152 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16409369 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/409369
Display substrate and method for manufacturing the same and display device May 9, 2019 Issued
Array ( [id] => 15299783 [patent_doc_number] => 20190393027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => Post Etch Defluorination Process [patent_app_type] => utility [patent_app_number] => 16/403722 [patent_app_country] => US [patent_app_date] => 2019-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6978 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16403722 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/403722
Post etch defluorination process May 5, 2019 Issued
Array ( [id] => 15857391 [patent_doc_number] => 10643994 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-05 [patent_title] => Package-embedded thin-film capacitors, package-integral magnetic inductors, and methods of assembling same [patent_app_type] => utility [patent_app_number] => 16/402588 [patent_app_country] => US [patent_app_date] => 2019-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6876 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16402588 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/402588
Package-embedded thin-film capacitors, package-integral magnetic inductors, and methods of assembling same May 2, 2019 Issued
Array ( [id] => 16424959 [patent_doc_number] => 20200350157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => TREATMENTS TO ENHANCE MATERIAL STRUCTURES [patent_app_type] => utility [patent_app_number] => 16/403312 [patent_app_country] => US [patent_app_date] => 2019-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5598 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16403312 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/403312
Treatments to enhance material structures May 2, 2019 Issued
Array ( [id] => 16048001 [patent_doc_number] => 10685883 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-06-16 [patent_title] => Method of wafer dicing and die [patent_app_type] => utility [patent_app_number] => 16/402216 [patent_app_country] => US [patent_app_date] => 2019-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 5176 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16402216 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/402216
Method of wafer dicing and die May 1, 2019 Issued
Array ( [id] => 15123385 [patent_doc_number] => 20190348326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => WAFER PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 16/400209 [patent_app_country] => US [patent_app_date] => 2019-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8105 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16400209 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/400209
Wafer processing method Apr 30, 2019 Issued
Array ( [id] => 16293610 [patent_doc_number] => 10770465 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-09-08 [patent_title] => Method used in forming integrated circuitry [patent_app_type] => utility [patent_app_number] => 16/399348 [patent_app_country] => US [patent_app_date] => 2019-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 5307 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16399348 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/399348
Method used in forming integrated circuitry Apr 29, 2019 Issued
Array ( [id] => 15030507 [patent_doc_number] => 20190326258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-24 [patent_title] => SYSTEM ON PACKAGE ARCHITECTURE INCLUDING STRUCTURES ON DIE BACK SIDE [patent_app_type] => utility [patent_app_number] => 16/399726 [patent_app_country] => US [patent_app_date] => 2019-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5148 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16399726 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/399726
System on package architecture including structures on die back side Apr 29, 2019 Issued
Array ( [id] => 15717667 [patent_doc_number] => 20200105601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => METHOD FOR MANUFACTURING CHIP PACKAGES [patent_app_type] => utility [patent_app_number] => 16/400016 [patent_app_country] => US [patent_app_date] => 2019-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2821 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16400016 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/400016
Method for manufacturing chip packages Apr 29, 2019 Issued
Array ( [id] => 15598427 [patent_doc_number] => 20200075748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => METHODS FOR FORMING SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/397577 [patent_app_country] => US [patent_app_date] => 2019-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6647 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16397577 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/397577
Methods for forming semiconductor structure Apr 28, 2019 Issued
Array ( [id] => 14676729 [patent_doc_number] => 20190237479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => MEMORY DEVICE AND METHOD FOR MANUFACTURING MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/381625 [patent_app_country] => US [patent_app_date] => 2019-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20559 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16381625 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/381625
Memory device and method for manufacturing memory device Apr 10, 2019 Issued
Array ( [id] => 15475753 [patent_doc_number] => 10553764 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-04 [patent_title] => Light-emitting dies incorporating wavelength-conversion materials and related methods [patent_app_type] => utility [patent_app_number] => 16/380736 [patent_app_country] => US [patent_app_date] => 2019-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 138 [patent_figures_cnt] => 138 [patent_no_of_words] => 48221 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16380736 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/380736
Light-emitting dies incorporating wavelength-conversion materials and related methods Apr 9, 2019 Issued
Array ( [id] => 14631687 [patent_doc_number] => 20190229215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-25 [patent_title] => Semiconductor Device and Method [patent_app_type] => utility [patent_app_number] => 16/372956 [patent_app_country] => US [patent_app_date] => 2019-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8372 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16372956 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/372956
Semiconductor device and method Apr 1, 2019 Issued
Array ( [id] => 16194371 [patent_doc_number] => 20200235220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/364210 [patent_app_country] => US [patent_app_date] => 2019-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4155 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16364210 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/364210
Semiconductor device and manufacturing method thereof Mar 25, 2019 Issued
Array ( [id] => 14938597 [patent_doc_number] => 20190304937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => DEVICES AND METHODS FOR ENHANCING INSERTION LOSS PERFORMANCE OF AN ANTENNA SWITCH [patent_app_type] => utility [patent_app_number] => 16/364439 [patent_app_country] => US [patent_app_date] => 2019-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4827 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16364439 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/364439
Devices and methods for enhancing insertion loss performance of an antenna switch Mar 25, 2019 Issued
Array ( [id] => 14938481 [patent_doc_number] => 20190304879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FORMANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/364517 [patent_app_country] => US [patent_app_date] => 2019-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9776 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16364517 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/364517
Semiconductor device having lead with back and end surfaces provided with plating layers Mar 25, 2019 Issued
Array ( [id] => 15123753 [patent_doc_number] => 20190348510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => SHIELDED TRENCH DEVICES [patent_app_type] => utility [patent_app_number] => 16/363812 [patent_app_country] => US [patent_app_date] => 2019-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11151 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -32 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16363812 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/363812
Shielded trench devices Mar 24, 2019 Issued
Array ( [id] => 16281934 [patent_doc_number] => 10764989 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-09-01 [patent_title] => Thermal enhancement of exposed die-down package [patent_app_type] => utility [patent_app_number] => 16/363556 [patent_app_country] => US [patent_app_date] => 2019-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 22 [patent_no_of_words] => 2566 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16363556 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/363556
Thermal enhancement of exposed die-down package Mar 24, 2019 Issued
Array ( [id] => 16172855 [patent_doc_number] => 10714432 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-07-14 [patent_title] => Layout to reduce noise in semiconductor devices [patent_app_type] => utility [patent_app_number] => 16/363114 [patent_app_country] => US [patent_app_date] => 2019-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 61 [patent_no_of_words] => 9298 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16363114 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/363114
Layout to reduce noise in semiconductor devices Mar 24, 2019 Issued
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