Search

George A. Goudreau

Examiner (ID: 143)

Most Active Art Unit
1763
Art Unit(s)
1109, 1304, 1792, 1763, 1104, 1765
Total Applications
1121
Issued Applications
962
Pending Applications
34
Abandoned Applications
125

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1180091 [patent_doc_number] => 06737202 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-18 [patent_title] => 'Method of fabricating a tiered structure using a multi-layered resist stack and use' [patent_app_type] => B2 [patent_app_number] => 10/081199 [patent_app_country] => US [patent_app_date] => 2002-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 4296 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/737/06737202.pdf [firstpage_image] =>[orig_patent_app_number] => 10081199 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/081199
Method of fabricating a tiered structure using a multi-layered resist stack and use Feb 21, 2002 Issued
Array ( [id] => 6706460 [patent_doc_number] => 20030153194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-14 [patent_title] => 'Plasma etching uniformity control' [patent_app_type] => new [patent_app_number] => 10/076129 [patent_app_country] => US [patent_app_date] => 2002-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2757 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20030153194.pdf [firstpage_image] =>[orig_patent_app_number] => 10076129 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/076129
Plasma etching uniformity control Feb 12, 2002 Issued
Array ( [id] => 1339737 [patent_doc_number] => 06586145 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-01 [patent_title] => 'Method of fabricating semiconductor device and semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/073189 [patent_app_country] => US [patent_app_date] => 2002-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 28 [patent_no_of_words] => 6277 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/586/06586145.pdf [firstpage_image] =>[orig_patent_app_number] => 10073189 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/073189
Method of fabricating semiconductor device and semiconductor device Feb 12, 2002 Issued
Array ( [id] => 1152938 [patent_doc_number] => 06758222 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-06 [patent_title] => 'Processing method for substrate' [patent_app_type] => B2 [patent_app_number] => 10/073429 [patent_app_country] => US [patent_app_date] => 2002-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2054 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/758/06758222.pdf [firstpage_image] =>[orig_patent_app_number] => 10073429 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/073429
Processing method for substrate Feb 10, 2002 Issued
Array ( [id] => 1034492 [patent_doc_number] => 06875701 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-05 [patent_title] => 'Nanotopography removing method' [patent_app_type] => utility [patent_app_number] => 10/062494 [patent_app_country] => US [patent_app_date] => 2002-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3472 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/875/06875701.pdf [firstpage_image] =>[orig_patent_app_number] => 10062494 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/062494
Nanotopography removing method Feb 4, 2002 Issued
Array ( [id] => 6081255 [patent_doc_number] => 20020081850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-27 [patent_title] => 'Method of fabricating a semiconductor device' [patent_app_type] => new [patent_app_number] => 10/060569 [patent_app_country] => US [patent_app_date] => 2002-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7609 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20020081850.pdf [firstpage_image] =>[orig_patent_app_number] => 10060569 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/060569
Method of fabricating a semiconductor device Jan 28, 2002 Issued
Array ( [id] => 1082357 [patent_doc_number] => 06833046 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-21 [patent_title] => 'Planarizing machines and methods for mechanical and/or chemical-mechanical planarization of microelectronic-device substrate assemblies' [patent_app_type] => B2 [patent_app_number] => 10/057600 [patent_app_country] => US [patent_app_date] => 2002-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4105 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/833/06833046.pdf [firstpage_image] =>[orig_patent_app_number] => 10057600 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/057600
Planarizing machines and methods for mechanical and/or chemical-mechanical planarization of microelectronic-device substrate assemblies Jan 23, 2002 Issued
Array ( [id] => 5986512 [patent_doc_number] => 20020098705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-25 [patent_title] => 'Single step chemical mechanical polish process to improve the surface roughness in MRAM technology' [patent_app_type] => new [patent_app_number] => 10/053019 [patent_app_country] => US [patent_app_date] => 2002-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2470 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20020098705.pdf [firstpage_image] =>[orig_patent_app_number] => 10053019 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/053019
Single step chemical mechanical polish process to improve the surface roughness in MRAM technology Jan 17, 2002 Abandoned
Array ( [id] => 5963544 [patent_doc_number] => 20020088537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-11 [patent_title] => 'Wafer scale molding of protective caps' [patent_app_type] => new [patent_app_number] => 10/043299 [patent_app_country] => US [patent_app_date] => 2002-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5152 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20020088537.pdf [firstpage_image] =>[orig_patent_app_number] => 10043299 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/043299
Wafer scale molding of protective caps Jan 13, 2002 Abandoned
Array ( [id] => 6503709 [patent_doc_number] => 20020134754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'Method for forming a shallow trench isolation' [patent_app_type] => new [patent_app_number] => 10/040523 [patent_app_country] => US [patent_app_date] => 2002-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4903 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20020134754.pdf [firstpage_image] =>[orig_patent_app_number] => 10040523 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/040523
Method of forming a shallow trench isolation Jan 6, 2002 Issued
Array ( [id] => 1267059 [patent_doc_number] => 06647994 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-18 [patent_title] => 'Method of resist stripping over low-k dielectric material' [patent_app_type] => B1 [patent_app_number] => 10/038709 [patent_app_country] => US [patent_app_date] => 2002-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1904 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/647/06647994.pdf [firstpage_image] =>[orig_patent_app_number] => 10038709 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/038709
Method of resist stripping over low-k dielectric material Jan 1, 2002 Issued
Array ( [id] => 6680669 [patent_doc_number] => 20030116533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'METHOD TO DECREASE FLUORINE CONTAMINATION IN LOW DIELECTRIC CONSTATNT FILMS' [patent_app_type] => new [patent_app_number] => 10/034859 [patent_app_country] => US [patent_app_date] => 2001-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1990 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20030116533.pdf [firstpage_image] =>[orig_patent_app_number] => 10034859 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/034859
Method to decrease fluorine contamination in low dielectric constant films Dec 19, 2001 Issued
Array ( [id] => 1095801 [patent_doc_number] => 06821792 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-23 [patent_title] => 'Method and apparatus for determining a sampling plan based on process and equipment state information' [patent_app_type] => B1 [patent_app_number] => 10/023119 [patent_app_country] => US [patent_app_date] => 2001-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3162 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/821/06821792.pdf [firstpage_image] =>[orig_patent_app_number] => 10023119 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/023119
Method and apparatus for determining a sampling plan based on process and equipment state information Dec 17, 2001 Issued
Array ( [id] => 1379160 [patent_doc_number] => 06547978 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-15 [patent_title] => 'Method of heating a semiconductor substrate' [patent_app_type] => B2 [patent_app_number] => 10/017001 [patent_app_country] => US [patent_app_date] => 2001-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 13390 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/547/06547978.pdf [firstpage_image] =>[orig_patent_app_number] => 10017001 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/017001
Method of heating a semiconductor substrate Dec 12, 2001 Issued
Array ( [id] => 1440147 [patent_doc_number] => 06495469 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'High selectivity, low etch depth micro-loading process for non stop layer damascene etch' [patent_app_type] => B1 [patent_app_number] => 09/999309 [patent_app_country] => US [patent_app_date] => 2001-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1828 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/495/06495469.pdf [firstpage_image] =>[orig_patent_app_number] => 09999309 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/999309
High selectivity, low etch depth micro-loading process for non stop layer damascene etch Dec 2, 2001 Issued
Array ( [id] => 6765788 [patent_doc_number] => 20030100188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-29 [patent_title] => 'METHOD OF FORMING DUAL DAMASCENE STRUCTURE' [patent_app_type] => new [patent_app_number] => 09/997339 [patent_app_country] => US [patent_app_date] => 2001-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3403 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20030100188.pdf [firstpage_image] =>[orig_patent_app_number] => 09997339 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/997339
Method of forming dual damascene structure Nov 26, 2001 Issued
Array ( [id] => 1407521 [patent_doc_number] => 06521080 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-18 [patent_title] => 'Method and apparatus for monitoring a process by employing principal component analysis' [patent_app_type] => B2 [patent_app_number] => 10/002830 [patent_app_country] => US [patent_app_date] => 2001-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 9584 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/521/06521080.pdf [firstpage_image] =>[orig_patent_app_number] => 10002830 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/002830
Method and apparatus for monitoring a process by employing principal component analysis Nov 14, 2001 Issued
Array ( [id] => 6861271 [patent_doc_number] => 20030092279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-15 [patent_title] => 'Method of forming a dual damascene via by using a metal hard mask layer' [patent_app_type] => new [patent_app_number] => 09/986929 [patent_app_country] => US [patent_app_date] => 2001-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3614 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 332 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20030092279.pdf [firstpage_image] =>[orig_patent_app_number] => 09986929 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/986929
Method of forming a dual damascene via by using a metal hard mask layer Nov 12, 2001 Issued
Array ( [id] => 1359186 [patent_doc_number] => 06573189 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-03 [patent_title] => 'Manufacture method of metal bottom ARC' [patent_app_type] => B1 [patent_app_number] => 10/044859 [patent_app_country] => US [patent_app_date] => 2001-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1334 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/573/06573189.pdf [firstpage_image] =>[orig_patent_app_number] => 10044859 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/044859
Manufacture method of metal bottom ARC Nov 6, 2001 Issued
Array ( [id] => 1056362 [patent_doc_number] => 06855585 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-15 [patent_title] => 'Integrating multiple thin film resistors' [patent_app_type] => utility [patent_app_number] => 10/002429 [patent_app_country] => US [patent_app_date] => 2001-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2458 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/855/06855585.pdf [firstpage_image] =>[orig_patent_app_number] => 10002429 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/002429
Integrating multiple thin film resistors Oct 30, 2001 Issued
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