Search

George B. Bennett

Examiner (ID: 2205, Phone: (571)272-2237 , Office: P/2855 )

Most Active Art Unit
2855
Art Unit(s)
2406, 2855, 3108, 3641, 2841, 2859, 2856
Total Applications
3542
Issued Applications
3139
Pending Applications
141
Abandoned Applications
302

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20292906 [patent_doc_number] => 20250318149 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-09 [patent_title] => 3D SEMICONDUCTOR DEVICE, STRUCTURE AND METHODS WITH MEMORY ARRAYS AND CONNECTIVITY STRUCTURES [patent_app_type] => utility [patent_app_number] => 19/245137 [patent_app_country] => US [patent_app_date] => 2025-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22051 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19245137 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/245137
3D SEMICONDUCTOR DEVICE, STRUCTURE AND METHODS WITH MEMORY ARRAYS AND CONNECTIVITY STRUCTURES Jun 19, 2025 Pending
Array ( [id] => 20096385 [patent_doc_number] => 20250226321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => TECHNIQUES, METHODS, AND STRUCTURES FOR RAPID AND EFFICIENT INTERCALATION-DOPING OF LARGE-AREA MULTI- LAYERED GRAPHENE SHEETS FOR TRANSPARENT CONDUCTOR APPLICATIONS, INCLUDING SOLAR CELLS AND DISPLAYS [patent_app_type] => utility [patent_app_number] => 19/059193 [patent_app_country] => US [patent_app_date] => 2025-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19059193 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/059193
Techniques, methods, and structures for rapid and efficient intercalation-doping of large-area multi-layered graphene sheets for transparent conductor applications, including solar cells and displays Feb 19, 2025 Issued
Array ( [id] => 20111594 [patent_doc_number] => 12362330 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => 3D semiconductor device and structure with connection paths [patent_app_type] => utility [patent_app_number] => 18/779059 [patent_app_country] => US [patent_app_date] => 2024-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 70 [patent_figures_cnt] => 89 [patent_no_of_words] => 38566 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18779059 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/779059
3D semiconductor device and structure with connection paths Jul 20, 2024 Issued
Array ( [id] => 20096384 [patent_doc_number] => 20250226320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => TECHNIQUES, METHODS, AND STRUCTURES FOR RAPID AND EFFICIENT INTERCALATION-DOPING OF LARGE-AREA MULTI- LAYERED GRAPHENE SHEETS FOR TRANSPARENT CONDUCTOR APPLICATIONS, INCLUDING SOLAR CELLS AND DISPLAYS [patent_app_type] => utility [patent_app_number] => 18/744533 [patent_app_country] => US [patent_app_date] => 2024-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18744533 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/744533
Techniques, methods, and structures for rapid and efficient intercalation-doping of large-area multi-layered graphene sheets for transparent conductor applications, including solar cells and displays Jun 13, 2024 Issued
Array ( [id] => 19751576 [patent_doc_number] => 20250040141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => 3D SEMICONDUCTOR DEVICE, STRUCTURE AND METHODS WITH MEMORY ARRAYS AND CONNECTIVITY STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/739083 [patent_app_country] => US [patent_app_date] => 2024-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25977 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18739083 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/739083
3D semiconductor device, structure and methods with memory arrays and connectivity structures Jun 9, 2024 Issued
Array ( [id] => 19468172 [patent_doc_number] => 20240321842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => PACKAGE-ON-PACKAGE (POP) SEMICONDUCTOR PACKAGE AND ELECTRONIC SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/733450 [patent_app_country] => US [patent_app_date] => 2024-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7010 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18733450 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/733450
PACKAGE-ON-PACKAGE (POP) SEMICONDUCTOR PACKAGE AND ELECTRONIC SYSTEM INCLUDING THE SAME Jun 3, 2024 Pending
Array ( [id] => 19452708 [patent_doc_number] => 20240312838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => METHOD AND IC DESIGN WITH NON-LINEAR POWER RAILS [patent_app_type] => utility [patent_app_number] => 18/672083 [patent_app_country] => US [patent_app_date] => 2024-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6590 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18672083 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/672083
METHOD AND IC DESIGN WITH NON-LINEAR POWER RAILS May 22, 2024 Pending
Array ( [id] => 19452930 [patent_doc_number] => 20240313060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => SEMICONDUCTOR DEVICE WITH FERROELECTRIC ALUMINUM NITRIDE [patent_app_type] => utility [patent_app_number] => 18/669392 [patent_app_country] => US [patent_app_date] => 2024-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6450 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18669392 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/669392
SEMICONDUCTOR DEVICE WITH FERROELECTRIC ALUMINUM NITRIDE May 19, 2024 Pending
Array ( [id] => 19436044 [patent_doc_number] => 20240304542 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => METHOD OF FABRICATING PACKAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/666798 [patent_app_country] => US [patent_app_date] => 2024-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9046 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18666798 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/666798
METHOD OF FABRICATING PACKAGE STRUCTURE May 15, 2024 Pending
Array ( [id] => 19420150 [patent_doc_number] => 20240296273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => INTEGRATED CIRCUIT, SYSTEM FOR AND METHOD OF FORMING AN INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/663652 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 39841 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18663652 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/663652
INTEGRATED CIRCUIT, SYSTEM FOR AND METHOD OF FORMING AN INTEGRATED CIRCUIT May 13, 2024 Pending
Array ( [id] => 19468081 [patent_doc_number] => 20240321751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/654111 [patent_app_country] => US [patent_app_date] => 2024-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10187 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18654111 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/654111
SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME May 2, 2024 Pending
Array ( [id] => 19337167 [patent_doc_number] => 20240251597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => DISPLAY PANEL AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/628541 [patent_app_country] => US [patent_app_date] => 2024-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19761 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18628541 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/628541
DISPLAY PANEL AND DISPLAY DEVICE Apr 4, 2024 Pending
Array ( [id] => 19384601 [patent_doc_number] => 20240274471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => SEMICONDUCTOR DEVICE WITH ELONGATED PATTERN [patent_app_type] => utility [patent_app_number] => 18/626229 [patent_app_country] => US [patent_app_date] => 2024-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19154 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18626229 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/626229
SEMICONDUCTOR DEVICE WITH ELONGATED PATTERN Apr 2, 2024 Pending
Array ( [id] => 19575132 [patent_doc_number] => 20240379424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => METHOD OF MAKING HIGH ASPECT RATIO OPENINGS IN A SEMICONDUCTOR DEVICE USING ION IMPLANTATED REGROWN CLADDING MASK [patent_app_type] => utility [patent_app_number] => 18/613834 [patent_app_country] => US [patent_app_date] => 2024-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12322 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18613834 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/613834
Method of making high aspect ratio openings in a semiconductor device using ion implanted regrown cladding mask Mar 21, 2024 Issued
Array ( [id] => 19639633 [patent_doc_number] => 12170248 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-17 [patent_title] => Graphene BEOL integration interconnection structures [patent_app_type] => utility [patent_app_number] => 18/607380 [patent_app_country] => US [patent_app_date] => 2024-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 7390 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18607380 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/607380
Graphene BEOL integration interconnection structures Mar 14, 2024 Issued
Array ( [id] => 20260562 [patent_doc_number] => 12432933 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Semiconductor packages [patent_app_type] => utility [patent_app_number] => 18/596625 [patent_app_country] => US [patent_app_date] => 2024-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 4420 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18596625 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/596625
Semiconductor packages Mar 5, 2024 Issued
Array ( [id] => 20198483 [patent_doc_number] => 20250275193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-28 [patent_title] => PUNCH THROUGH LEAKAGE CONTROL FOR SEMICONDUCTOR STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/587430 [patent_app_country] => US [patent_app_date] => 2024-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3202 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18587430 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/587430
PUNCH THROUGH LEAKAGE CONTROL FOR SEMICONDUCTOR STRUCTURES Feb 25, 2024 Pending
Array ( [id] => 19788559 [patent_doc_number] => 20250062238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => SEMICONDUCTOR PACKAGE AND INTEGRATED CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 18/587264 [patent_app_country] => US [patent_app_date] => 2024-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9775 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18587264 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/587264
SEMICONDUCTOR PACKAGE AND INTEGRATED CIRCUIT DEVICE Feb 25, 2024 Pending
Array ( [id] => 20268687 [patent_doc_number] => 12439701 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Power cell for semiconductor devices [patent_app_type] => utility [patent_app_number] => 18/586918 [patent_app_country] => US [patent_app_date] => 2024-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7548 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18586918 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/586918
Power cell for semiconductor devices Feb 25, 2024 Issued
Array ( [id] => 19237455 [patent_doc_number] => 20240194650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => MULTI-WAFER INTEGRATION [patent_app_type] => utility [patent_app_number] => 18/587406 [patent_app_country] => US [patent_app_date] => 2024-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7421 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18587406 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/587406
Multi-wafer integration Feb 25, 2024 Issued
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