Search

George C. Eckert Ii

Examiner (ID: 1793)

Most Active Art Unit
2815
Art Unit(s)
2815
Total Applications
416
Issued Applications
363
Pending Applications
8
Abandoned Applications
45

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4183884 [patent_doc_number] => 06037623 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Polycrystalline silicon resistors for integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/174869 [patent_app_country] => US [patent_app_date] => 1998-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2283 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/037/06037623.pdf [firstpage_image] =>[orig_patent_app_number] => 174869 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/174869
Polycrystalline silicon resistors for integrated circuits Oct 18, 1998 Issued
Array ( [id] => 1582954 [patent_doc_number] => 06424010 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Method of manufacturing a semiconductor device having reduced power consumption without a reduction in the source/drain breakdown voltage' [patent_app_type] => B1 [patent_app_number] => 09/169903 [patent_app_country] => US [patent_app_date] => 1998-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 46 [patent_no_of_words] => 10868 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/424/06424010.pdf [firstpage_image] =>[orig_patent_app_number] => 09169903 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/169903
Method of manufacturing a semiconductor device having reduced power consumption without a reduction in the source/drain breakdown voltage Oct 8, 1998 Issued
09/164343 SEMICONDUCTOR DEVICE HAVING METAL SILICIDE FILMS COVERING BOTH THE GATE ELECTRODE AND SOURCE-DRAIN DIFFUSION LAYERS Sep 30, 1998 Abandoned
Array ( [id] => 4264812 [patent_doc_number] => 06204537 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'ESD protection scheme' [patent_app_type] => 1 [patent_app_number] => 9/164301 [patent_app_country] => US [patent_app_date] => 1998-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 4696 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204537.pdf [firstpage_image] =>[orig_patent_app_number] => 164301 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/164301
ESD protection scheme Sep 30, 1998 Issued
Array ( [id] => 3979906 [patent_doc_number] => 06003311 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Stator blade of torque converter' [patent_app_type] => 1 [patent_app_number] => 9/164643 [patent_app_country] => US [patent_app_date] => 1998-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4999 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/003/06003311.pdf [firstpage_image] =>[orig_patent_app_number] => 164643 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/164643
Stator blade of torque converter Sep 30, 1998 Issued
Array ( [id] => 4119750 [patent_doc_number] => 06046469 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Semiconductor storage device having a capacitor and a MOS transistor' [patent_app_type] => 1 [patent_app_number] => 9/161483 [patent_app_country] => US [patent_app_date] => 1998-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3237 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/046/06046469.pdf [firstpage_image] =>[orig_patent_app_number] => 161483 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/161483
Semiconductor storage device having a capacitor and a MOS transistor Sep 27, 1998 Issued
09/151173 MOS CONTROL DIODE AND METHOD FOR MANUFACTURING THE SAME Sep 9, 1998 Abandoned
Array ( [id] => 6221856 [patent_doc_number] => 20020003252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-10 [patent_title] => 'FLASH MEMORY CIRCUIT WITH WITH RESISTANCE TO DISTURB EFFECT' [patent_app_type] => new [patent_app_number] => 09/145873 [patent_app_country] => US [patent_app_date] => 1998-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2497 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 25 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20020003252.pdf [firstpage_image] =>[orig_patent_app_number] => 09145873 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/145873
FLASH MEMORY CIRCUIT WITH WITH RESISTANCE TO DISTURB EFFECT Sep 2, 1998 Abandoned
Array ( [id] => 1509441 [patent_doc_number] => 06441466 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Method and apparatus for reducing fixed charge in semiconductor device layers' [patent_app_type] => B1 [patent_app_number] => 09/145723 [patent_app_country] => US [patent_app_date] => 1998-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2182 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/441/06441466.pdf [firstpage_image] =>[orig_patent_app_number] => 09145723 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/145723
Method and apparatus for reducing fixed charge in semiconductor device layers Sep 1, 1998 Issued
Array ( [id] => 4197604 [patent_doc_number] => 06043544 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Semiconductor gate conductor with a substantially uniform doping profile having minimal susceptibility to dopant penetration into the underlying gate dielectric' [patent_app_type] => 1 [patent_app_number] => 9/140202 [patent_app_country] => US [patent_app_date] => 1998-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3513 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/043/06043544.pdf [firstpage_image] =>[orig_patent_app_number] => 140202 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/140202
Semiconductor gate conductor with a substantially uniform doping profile having minimal susceptibility to dopant penetration into the underlying gate dielectric Aug 25, 1998 Issued
Array ( [id] => 4070553 [patent_doc_number] => 06008523 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Electrical fuses with tight pitches and method of fabrication in semiconductors' [patent_app_type] => 1 [patent_app_number] => 9/140573 [patent_app_country] => US [patent_app_date] => 1998-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 7266 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/008/06008523.pdf [firstpage_image] =>[orig_patent_app_number] => 140573 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/140573
Electrical fuses with tight pitches and method of fabrication in semiconductors Aug 25, 1998 Issued
Array ( [id] => 4411001 [patent_doc_number] => 06271590 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Graded layer for use in semiconductor circuits and method for making same' [patent_app_type] => 1 [patent_app_number] => 9/138811 [patent_app_country] => US [patent_app_date] => 1998-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3223 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271590.pdf [firstpage_image] =>[orig_patent_app_number] => 138811 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/138811
Graded layer for use in semiconductor circuits and method for making same Aug 20, 1998 Issued
Array ( [id] => 4257479 [patent_doc_number] => 06208004 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Semiconductor device with high-temperature-stable gate electrode for sub-micron applications and fabrication thereof' [patent_app_type] => 1 [patent_app_number] => 9/136482 [patent_app_country] => US [patent_app_date] => 1998-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4467 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/208/06208004.pdf [firstpage_image] =>[orig_patent_app_number] => 136482 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/136482
Semiconductor device with high-temperature-stable gate electrode for sub-micron applications and fabrication thereof Aug 18, 1998 Issued
Array ( [id] => 4277773 [patent_doc_number] => 06323520 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Method for forming channel-region doping profile for semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/127582 [patent_app_country] => US [patent_app_date] => 1998-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4015 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323520.pdf [firstpage_image] =>[orig_patent_app_number] => 127582 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/127582
Method for forming channel-region doping profile for semiconductor device Jul 30, 1998 Issued
Array ( [id] => 4163613 [patent_doc_number] => 06114767 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'EEPROM semiconductor device and method of fabricating the same' [patent_app_type] => 1 [patent_app_number] => 9/124851 [patent_app_country] => US [patent_app_date] => 1998-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 28 [patent_no_of_words] => 6545 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114767.pdf [firstpage_image] =>[orig_patent_app_number] => 124851 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/124851
EEPROM semiconductor device and method of fabricating the same Jul 29, 1998 Issued
Array ( [id] => 4363503 [patent_doc_number] => 06169306 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Semiconductor devices comprised of one or more epitaxial layers' [patent_app_type] => 1 [patent_app_number] => 9/122833 [patent_app_country] => US [patent_app_date] => 1998-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5084 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/169/06169306.pdf [firstpage_image] =>[orig_patent_app_number] => 122833 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/122833
Semiconductor devices comprised of one or more epitaxial layers Jul 26, 1998 Issued
09/118231 SELF-ALIGNED FUSE STRUCTURE AND METHOD WITH DUAL-THICKNESS DIELECTRIC Jul 16, 1998 Abandoned
Array ( [id] => 4266024 [patent_doc_number] => 06259146 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Self-aligned fuse structure and method with heat sink' [patent_app_type] => 1 [patent_app_number] => 9/118232 [patent_app_country] => US [patent_app_date] => 1998-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 6356 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/259/06259146.pdf [firstpage_image] =>[orig_patent_app_number] => 118232 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/118232
Self-aligned fuse structure and method with heat sink Jul 16, 1998 Issued
Array ( [id] => 4325116 [patent_doc_number] => 06249054 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Semiconductor memory device with a stacked capacitance structure' [patent_app_type] => 1 [patent_app_number] => 9/110888 [patent_app_country] => US [patent_app_date] => 1998-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 11407 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 357 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249054.pdf [firstpage_image] =>[orig_patent_app_number] => 110888 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/110888
Semiconductor memory device with a stacked capacitance structure Jul 6, 1998 Issued
Array ( [id] => 4162698 [patent_doc_number] => 06157060 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'High density integrated semiconductor memory and method for producing the memory' [patent_app_type] => 1 [patent_app_number] => 9/111120 [patent_app_country] => US [patent_app_date] => 1998-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3216 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157060.pdf [firstpage_image] =>[orig_patent_app_number] => 111120 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/111120
High density integrated semiconductor memory and method for producing the memory Jul 5, 1998 Issued
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