George C. Eckert Ii

Array ( [id] => 4090556 [patent_doc_number] => 06025614 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Amplifier semiconductor element, method for fabricating the same, and amplifier semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/050431 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 32 [patent_no_of_words] => 8021 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/025/06025614.pdf [firstpage_image] =>[orig_patent_app_number] => 050431 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3940353 [patent_doc_number] => 05929493 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'CMOS transistors with self-aligned planarization twin-well by using fewer mask counts' [patent_app_type] => 1 [patent_app_number] => 9/052280 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 2368 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/929/05929493.pdf [firstpage_image] =>[orig_patent_app_number] => 052280 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4179632 [patent_doc_number] => 06084265 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'High density shallow trench contactless nonvolitile memory' [patent_app_type] => 1 [patent_app_number] => 9/050540 [patent_app_country] => US [patent_app_date] => 1998-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2877 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/084/06084265.pdf [firstpage_image] =>[orig_patent_app_number] => 050540 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4422645 [patent_doc_number] => 06194770 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Photo receptor with reduced noise' [patent_app_type] => 1 [patent_app_number] => 9/039833 [patent_app_country] => US [patent_app_date] => 1998-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2848 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/194/06194770.pdf [firstpage_image] =>[orig_patent_app_number] => 039833 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4242460 [patent_doc_number] => 06144062 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Semiconductor device having thin electrode layer adjacent gate insulator and method of manufacture' [patent_app_type] => 1 [patent_app_number] => 9/041793 [patent_app_country] => US [patent_app_date] => 1998-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 29 [patent_no_of_words] => 14274 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/144/06144062.pdf [firstpage_image] =>[orig_patent_app_number] => 041793 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4364487 [patent_doc_number] => 06191455 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Semi-conductor device protected by electrostatic protection device from electrostatic discharge damage' [patent_app_type] => 1 [patent_app_number] => 9/038966 [patent_app_country] => US [patent_app_date] => 1998-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 6710 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/191/06191455.pdf [firstpage_image] =>[orig_patent_app_number] => 038966 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4331613 [patent_doc_number] => 06329688 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Nonvolatile semiconductor memory device and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/037031 [patent_app_country] => US [patent_app_date] => 1998-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 47 [patent_no_of_words] => 10661 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/329/06329688.pdf [firstpage_image] =>[orig_patent_app_number] => 037031 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4363409 [patent_doc_number] => 06169300 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Insulated gate bipolar transistor with high dynamic ruggedness' [patent_app_type] => 1 [patent_app_number] => 9/034391 [patent_app_country] => US [patent_app_date] => 1998-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2207 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/169/06169300.pdf [firstpage_image] =>[orig_patent_app_number] => 034391 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4161175 [patent_doc_number] => 06107659 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Nonvolatile semiconductor memory device operable at high speed with low power supply voltage while preventing overerasing/overwriting' [patent_app_type] => 1 [patent_app_number] => 9/033581 [patent_app_country] => US [patent_app_date] => 1998-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 75 [patent_no_of_words] => 23075 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 378 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/107/06107659.pdf [firstpage_image] =>[orig_patent_app_number] => 033581 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1537165 [patent_doc_number] => 06337504 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-08 [patent_title] => 'Insulated gate transistor with leakage current prevention feature' [patent_app_type] => B1 [patent_app_number] => 09/031733 [patent_app_country] => US [patent_app_date] => 1998-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 5241 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/337/06337504.pdf [firstpage_image] =>[orig_patent_app_number] => 09031733 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4189549 [patent_doc_number] => 06150706 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Capacitor/antifuse structure having a barrier-layer electrode and improved barrier layer' [patent_app_type] => 1 [patent_app_number] => 9/032182 [patent_app_country] => US [patent_app_date] => 1998-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4032 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/150/06150706.pdf [firstpage_image] =>[orig_patent_app_number] => 032182 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4140548 [patent_doc_number] => 06015990 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-18 [patent_title] => 'Semiconductor memory device and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/030809 [patent_app_country] => US [patent_app_date] => 1998-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 31 [patent_no_of_words] => 16989 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/015/06015990.pdf [firstpage_image] =>[orig_patent_app_number] => 030809 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4243664 [patent_doc_number] => 06080998 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Amorphous silicon germanium thin film and photovoltaic element' [patent_app_type] => 1 [patent_app_number] => 9/030691 [patent_app_country] => US [patent_app_date] => 1998-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6299 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/080/06080998.pdf [firstpage_image] =>[orig_patent_app_number] => 030691 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4017039 [patent_doc_number] => 05962894 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Trench transistor with metal spacers' [patent_app_type] => 1 [patent_app_number] => 9/030052 [patent_app_country] => US [patent_app_date] => 1998-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 33 [patent_no_of_words] => 7306 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/962/05962894.pdf [firstpage_image] =>[orig_patent_app_number] => 030052 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4183966 [patent_doc_number] => 06037629 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Trench transistor and isolation trench' [patent_app_type] => 1 [patent_app_number] => 9/028895 [patent_app_country] => US [patent_app_date] => 1998-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 5054 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/037/06037629.pdf [firstpage_image] =>[orig_patent_app_number] => 028895 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3944210 [patent_doc_number] => 05973365 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'MOS transistor and lateral insulating method of a MOS transistor active region' [patent_app_type] => 1 [patent_app_number] => 9/011751 [patent_app_country] => US [patent_app_date] => 1998-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3511 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/973/05973365.pdf [firstpage_image] =>[orig_patent_app_number] => 011751 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4070525 [patent_doc_number] => 06008521 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Integrated circuit employing simultaneously formed isolation and transistor trenches' [patent_app_type] => 1 [patent_app_number] => 9/027573 [patent_app_country] => US [patent_app_date] => 1998-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 6409 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/008/06008521.pdf [firstpage_image] =>[orig_patent_app_number] => 027573 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1340497 [patent_doc_number] => 06593617 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-15 [patent_title] => 'Field effect transistors with vertical gate side walls and method for making such transistors' [patent_app_type] => B1 [patent_app_number] => 09/026093 [patent_app_country] => US [patent_app_date] => 1998-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 5286 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/593/06593617.pdf [firstpage_image] =>[orig_patent_app_number] => 09026093 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4038045 [patent_doc_number] => 05994747 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'MOSFETs with recessed self-aligned silicide gradual S/D junction' [patent_app_type] => 1 [patent_app_number] => 9/023454 [patent_app_country] => US [patent_app_date] => 1998-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2971 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/994/05994747.pdf [firstpage_image] =>[orig_patent_app_number] => 023454 [rel_patent_id] =>[rel_patent_doc_number] =>)