Search

George C. Manuel

Examiner (ID: 4088, Phone: (571)272-4952 , Office: P/3762 )

Most Active Art Unit
3762
Art Unit(s)
3727, 3737, 3305, 2899, 3792, 3762, 3711
Total Applications
4175
Issued Applications
3592
Pending Applications
314
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
07/900516 METHOD AND APPARATUS FOR OPTIMIZING ELECTRONIC CIRCUITS Jun 16, 1992 Abandoned
Array ( [id] => 3589999 [patent_doc_number] => 05499191 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-12 [patent_title] => 'Multi-level logic optimization in programmable logic devices' [patent_app_type] => 1 [patent_app_number] => 7/898955 [patent_app_country] => US [patent_app_date] => 1992-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 18767 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/499/05499191.pdf [firstpage_image] =>[orig_patent_app_number] => 898955 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/898955
Multi-level logic optimization in programmable logic devices Jun 14, 1992 Issued
Array ( [id] => 3049083 [patent_doc_number] => 05377123 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-27 [patent_title] => 'Programmable logic device' [patent_app_type] => 1 [patent_app_number] => 7/895607 [patent_app_country] => US [patent_app_date] => 1992-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 38 [patent_no_of_words] => 31560 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/377/05377123.pdf [firstpage_image] =>[orig_patent_app_number] => 895607 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/895607
Programmable logic device Jun 7, 1992 Issued
Array ( [id] => 3483255 [patent_doc_number] => 05428550 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-27 [patent_title] => 'Hierarchical hardware flowchart using symbolic macros' [patent_app_type] => 1 [patent_app_number] => 7/893434 [patent_app_country] => US [patent_app_date] => 1992-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 28 [patent_no_of_words] => 3307 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/428/05428550.pdf [firstpage_image] =>[orig_patent_app_number] => 893434 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/893434
Hierarchical hardware flowchart using symbolic macros Jun 3, 1992 Issued
Array ( [id] => 3482050 [patent_doc_number] => 05477467 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-19 [patent_title] => 'Shrinkable BiCMOS circuit layout' [patent_app_type] => 1 [patent_app_number] => 7/891902 [patent_app_country] => US [patent_app_date] => 1992-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1905 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/477/05477467.pdf [firstpage_image] =>[orig_patent_app_number] => 891902 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/891902
Shrinkable BiCMOS circuit layout May 31, 1992 Issued
07/884638 AIRCRAFT WEIGHT AND CENTER OF GRAVITY INDICATOR May 14, 1992 Abandoned
Array ( [id] => 2957979 [patent_doc_number] => 05222033 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-22 [patent_title] => 'Method of retrieving frames on a microfiche using arbitrarily designated frames' [patent_app_type] => 1 [patent_app_number] => 7/873612 [patent_app_country] => US [patent_app_date] => 1992-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4460 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/222/05222033.pdf [firstpage_image] =>[orig_patent_app_number] => 873612 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/873612
Method of retrieving frames on a microfiche using arbitrarily designated frames Apr 16, 1992 Issued
Array ( [id] => 3897408 [patent_doc_number] => 05715178 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-03 [patent_title] => 'Method of validating measurement data of a process parameter from a plurality of individual sensor inputs' [patent_app_type] => 1 [patent_app_number] => 7/870455 [patent_app_country] => US [patent_app_date] => 1992-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 45 [patent_no_of_words] => 25168 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/715/05715178.pdf [firstpage_image] =>[orig_patent_app_number] => 870455 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/870455
Method of validating measurement data of a process parameter from a plurality of individual sensor inputs Apr 14, 1992 Issued
Array ( [id] => 2903968 [patent_doc_number] => 05272648 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-21 [patent_title] => 'Method of detecting a position of a robot' [patent_app_type] => 1 [patent_app_number] => 7/864297 [patent_app_country] => US [patent_app_date] => 1992-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2480 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 345 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/272/05272648.pdf [firstpage_image] =>[orig_patent_app_number] => 864297 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/864297
Method of detecting a position of a robot Apr 5, 1992 Issued
Array ( [id] => 3435269 [patent_doc_number] => 05404312 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Automatic designing system capable of designing a logic circuit as desired' [patent_app_type] => 1 [patent_app_number] => 7/863772 [patent_app_country] => US [patent_app_date] => 1992-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2921 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/404/05404312.pdf [firstpage_image] =>[orig_patent_app_number] => 863772 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/863772
Automatic designing system capable of designing a logic circuit as desired Apr 5, 1992 Issued
07/866082 ONBOARD NAVIGATIONAL SYSTEM Apr 2, 1992 Abandoned
Array ( [id] => 3466360 [patent_doc_number] => 05402356 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-28 [patent_title] => 'Buffer circuit design using back track searching of site trees' [patent_app_type] => 1 [patent_app_number] => 7/862895 [patent_app_country] => US [patent_app_date] => 1992-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 7923 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 359 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/402/05402356.pdf [firstpage_image] =>[orig_patent_app_number] => 862895 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/862895
Buffer circuit design using back track searching of site trees Apr 1, 1992 Issued
Array ( [id] => 3032451 [patent_doc_number] => 05303348 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-12 [patent_title] => 'Method of arbitrating access to a data bus and apparatus therefor' [patent_app_type] => 1 [patent_app_number] => 7/856430 [patent_app_country] => US [patent_app_date] => 1992-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 38 [patent_no_of_words] => 13668 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/303/05303348.pdf [firstpage_image] =>[orig_patent_app_number] => 856430 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/856430
Method of arbitrating access to a data bus and apparatus therefor Mar 22, 1992 Issued
Array ( [id] => 3658816 [patent_doc_number] => 05684721 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-04 [patent_title] => 'Electronic systems and emulation and testing devices, cables, systems and methods' [patent_app_type] => 1 [patent_app_number] => 7/851232 [patent_app_country] => US [patent_app_date] => 1992-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 27 [patent_no_of_words] => 18440 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/684/05684721.pdf [firstpage_image] =>[orig_patent_app_number] => 851232 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/851232
Electronic systems and emulation and testing devices, cables, systems and methods Mar 12, 1992 Issued
Array ( [id] => 3418861 [patent_doc_number] => 05461577 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-24 [patent_title] => 'Comprehensive logic circuit layout system' [patent_app_type] => 1 [patent_app_number] => 7/845302 [patent_app_country] => US [patent_app_date] => 1992-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 30 [patent_no_of_words] => 22013 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/461/05461577.pdf [firstpage_image] =>[orig_patent_app_number] => 845302 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/845302
Comprehensive logic circuit layout system Mar 2, 1992 Issued
Array ( [id] => 2904870 [patent_doc_number] => 05241486 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-31 [patent_title] => 'Methods and apparatus for marking and identifying hooks of electric motors' [patent_app_type] => 1 [patent_app_number] => 7/841083 [patent_app_country] => US [patent_app_date] => 1992-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 3193 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/241/05241486.pdf [firstpage_image] =>[orig_patent_app_number] => 841083 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/841083
Methods and apparatus for marking and identifying hooks of electric motors Feb 24, 1992 Issued
Array ( [id] => 2879618 [patent_doc_number] => 05153834 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-06 [patent_title] => 'Method and apparatus for detecting a misfire in a combustion chamber of an internal combustion engine' [patent_app_type] => 1 [patent_app_number] => 7/831633 [patent_app_country] => US [patent_app_date] => 1992-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 3919 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/153/05153834.pdf [firstpage_image] =>[orig_patent_app_number] => 831633 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/831633
Method and apparatus for detecting a misfire in a combustion chamber of an internal combustion engine Feb 9, 1992 Issued
Array ( [id] => 3435227 [patent_doc_number] => 05404309 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Cad apparatus for designing pattern of electric circuit' [patent_app_type] => 1 [patent_app_number] => 7/830424 [patent_app_country] => US [patent_app_date] => 1992-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 8101 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 376 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/404/05404309.pdf [firstpage_image] =>[orig_patent_app_number] => 830424 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/830424
Cad apparatus for designing pattern of electric circuit Jan 30, 1992 Issued
Array ( [id] => 2885359 [patent_doc_number] => 05185693 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-09 [patent_title] => 'Method and apparatus for providing backup process control' [patent_app_type] => 1 [patent_app_number] => 7/827920 [patent_app_country] => US [patent_app_date] => 1992-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5129 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/185/05185693.pdf [firstpage_image] =>[orig_patent_app_number] => 827920 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/827920
Method and apparatus for providing backup process control Jan 28, 1992 Issued
Array ( [id] => 3128350 [patent_doc_number] => 05450331 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-12 [patent_title] => 'Method for verifying circuit layout design' [patent_app_type] => 1 [patent_app_number] => 7/825490 [patent_app_country] => US [patent_app_date] => 1992-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2609 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/450/05450331.pdf [firstpage_image] =>[orig_patent_app_number] => 825490 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/825490
Method for verifying circuit layout design Jan 23, 1992 Issued
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