Search

George C. Manuel

Examiner (ID: 4088, Phone: (571)272-4952 , Office: P/3762 )

Most Active Art Unit
3762
Art Unit(s)
3727, 3737, 3305, 2899, 3792, 3762, 3711
Total Applications
4175
Issued Applications
3592
Pending Applications
314
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3066506 [patent_doc_number] => 05351197 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-27 [patent_title] => 'Method and apparatus for designing the layout of a subcircuit in an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 7/824707 [patent_app_country] => US [patent_app_date] => 1992-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 7242 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/351/05351197.pdf [firstpage_image] =>[orig_patent_app_number] => 824707 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/824707
Method and apparatus for designing the layout of a subcircuit in an integrated circuit Jan 20, 1992 Issued
Array ( [id] => 2908172 [patent_doc_number] => 05245550 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-14 [patent_title] => 'Apparatus for wire routing of VLSI' [patent_app_type] => 1 [patent_app_number] => 7/820995 [patent_app_country] => US [patent_app_date] => 1992-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 9364 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 417 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/245/05245550.pdf [firstpage_image] =>[orig_patent_app_number] => 820995 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/820995
Apparatus for wire routing of VLSI Jan 14, 1992 Issued
07/818352 FRANKING MACHINE SYSTEM Jan 8, 1992 Abandoned
Array ( [id] => 2896040 [patent_doc_number] => 05214584 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-05-25 [patent_title] => 'Bidirectional data interface for a processor embedded in a self-propelled vehicle' [patent_app_type] => 1 [patent_app_number] => 7/815894 [patent_app_country] => US [patent_app_date] => 1991-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4609 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/214/05214584.pdf [firstpage_image] =>[orig_patent_app_number] => 815894 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/815894
Bidirectional data interface for a processor embedded in a self-propelled vehicle Dec 30, 1991 Issued
Array ( [id] => 2912832 [patent_doc_number] => 05249134 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-28 [patent_title] => 'Method of layout processing including layout data verification' [patent_app_type] => 1 [patent_app_number] => 7/810353 [patent_app_country] => US [patent_app_date] => 1991-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 1706 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/249/05249134.pdf [firstpage_image] =>[orig_patent_app_number] => 810353 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/810353
Method of layout processing including layout data verification Dec 17, 1991 Issued
Array ( [id] => 3466383 [patent_doc_number] => 05402357 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-28 [patent_title] => 'System and method for synthesizing logic circuits with timing constraints' [patent_app_type] => 1 [patent_app_number] => 7/801793 [patent_app_country] => US [patent_app_date] => 1991-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4586 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/402/05402357.pdf [firstpage_image] =>[orig_patent_app_number] => 801793 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/801793
System and method for synthesizing logic circuits with timing constraints Dec 1, 1991 Issued
07/799693 METHOD AND APPARATUS FOR DISPLAYING PROCESS END POINT SIGNAL BASED ON EMISSION CONCENTRATION WITHIN A PROCESSING CHAMBER Nov 24, 1991 Abandoned
Array ( [id] => 3430397 [patent_doc_number] => 05390130 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-14 [patent_title] => 'Camera battery checking apparatus' [patent_app_type] => 1 [patent_app_number] => 7/793614 [patent_app_country] => US [patent_app_date] => 1991-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 4907 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/390/05390130.pdf [firstpage_image] =>[orig_patent_app_number] => 793614 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/793614
Camera battery checking apparatus Nov 17, 1991 Issued
07/793106 SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION METHOD Nov 14, 1991 Issued
Array ( [id] => 3463696 [patent_doc_number] => 05452227 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-19 [patent_title] => 'Method and apparatus for converting a programmable logic device designed into a selectable target gate array design' [patent_app_type] => 1 [patent_app_number] => 7/790920 [patent_app_country] => US [patent_app_date] => 1991-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4775 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/452/05452227.pdf [firstpage_image] =>[orig_patent_app_number] => 790920 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/790920
Method and apparatus for converting a programmable logic device designed into a selectable target gate array design Nov 12, 1991 Issued
Array ( [id] => 3130416 [patent_doc_number] => 05384711 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-24 [patent_title] => 'Method of and apparatus for inspecting pattern on printed board' [patent_app_type] => 1 [patent_app_number] => 7/791063 [patent_app_country] => US [patent_app_date] => 1991-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 4933 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/384/05384711.pdf [firstpage_image] =>[orig_patent_app_number] => 791063 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/791063
Method of and apparatus for inspecting pattern on printed board Nov 11, 1991 Issued
07/786450 DRIVER PREFERENCE RESPONSIVE VEHICLE ROUTE GUIDANCE SYSTEM Oct 31, 1991 Abandoned
Array ( [id] => 2952544 [patent_doc_number] => 05224056 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-29 [patent_title] => 'Logic placement using positionally asymmetrical partitioning algorithm' [patent_app_type] => 1 [patent_app_number] => 7/784844 [patent_app_country] => US [patent_app_date] => 1991-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 32 [patent_no_of_words] => 11296 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/224/05224056.pdf [firstpage_image] =>[orig_patent_app_number] => 784844 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/784844
Logic placement using positionally asymmetrical partitioning algorithm Oct 29, 1991 Issued
Array ( [id] => 3103561 [patent_doc_number] => 05369593 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-29 [patent_title] => 'System for and method of connecting a hardware modeling element to a hardware modeling system' [patent_app_type] => 1 [patent_app_number] => 7/780529 [patent_app_country] => US [patent_app_date] => 1991-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 24 [patent_no_of_words] => 9295 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/369/05369593.pdf [firstpage_image] =>[orig_patent_app_number] => 780529 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/780529
System for and method of connecting a hardware modeling element to a hardware modeling system Oct 17, 1991 Issued
Array ( [id] => 3504135 [patent_doc_number] => 05508918 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-16 [patent_title] => 'Predictor/check crash discriminator' [patent_app_type] => 1 [patent_app_number] => 7/773017 [patent_app_country] => US [patent_app_date] => 1991-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3298 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/508/05508918.pdf [firstpage_image] =>[orig_patent_app_number] => 773017 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/773017
Predictor/check crash discriminator Oct 7, 1991 Issued
Array ( [id] => 2930992 [patent_doc_number] => 05235521 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-10 [patent_title] => 'Reducing clock skew in large-scale integrated circuits' [patent_app_type] => 1 [patent_app_number] => 7/773061 [patent_app_country] => US [patent_app_date] => 1991-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6209 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/235/05235521.pdf [firstpage_image] =>[orig_patent_app_number] => 773061 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/773061
Reducing clock skew in large-scale integrated circuits Oct 7, 1991 Issued
Array ( [id] => 3012183 [patent_doc_number] => 05371683 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-06 [patent_title] => 'LSI design support system' [patent_app_type] => 1 [patent_app_number] => 7/769592 [patent_app_country] => US [patent_app_date] => 1991-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 8613 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/371/05371683.pdf [firstpage_image] =>[orig_patent_app_number] => 769592 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/769592
LSI design support system Oct 2, 1991 Issued
Array ( [id] => 3018747 [patent_doc_number] => 05331569 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-19 [patent_title] => 'Method and system for logic change in an automatic logic synthesis system' [patent_app_type] => 1 [patent_app_number] => 7/764576 [patent_app_country] => US [patent_app_date] => 1991-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4227 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/331/05331569.pdf [firstpage_image] =>[orig_patent_app_number] => 764576 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/764576
Method and system for logic change in an automatic logic synthesis system Sep 23, 1991 Issued
07/764263 UNIVERSAL INTERCONNECT MATRIX ARRAY Sep 22, 1991 Abandoned
Array ( [id] => 2979076 [patent_doc_number] => 05258932 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-02 [patent_title] => 'PLA simulation method' [patent_app_type] => 1 [patent_app_number] => 7/759368 [patent_app_country] => US [patent_app_date] => 1991-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4065 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/258/05258932.pdf [firstpage_image] =>[orig_patent_app_number] => 759368 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/759368
PLA simulation method Sep 12, 1991 Issued
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