Search

George D Kirschbaum

Examiner (ID: 18162, Phone: (571)272-4232 , Office: P/2913 )

Most Active Art Unit
2913
Art Unit(s)
2922, 2913
Total Applications
3416
Issued Applications
3259
Pending Applications
8
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10358664 [patent_doc_number] => 20150243669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-27 [patent_title] => 'MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/708297 [patent_app_country] => US [patent_app_date] => 2015-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3743 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14708297 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/708297
MEMORY DEVICE May 10, 2015 Abandoned
Array ( [id] => 10464109 [patent_doc_number] => 20150349124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'TRANSISTOR STRUCTURE HAVING BURIED ISLAND REGIONS' [patent_app_type] => utility [patent_app_number] => 14/706350 [patent_app_country] => US [patent_app_date] => 2015-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3725 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14706350 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/706350
Transistor structure having buried island regions May 6, 2015 Issued
Array ( [id] => 10315170 [patent_doc_number] => 20150200174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-16 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/669219 [patent_app_country] => US [patent_app_date] => 2015-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3184 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14669219 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/669219
Semiconductor device Mar 25, 2015 Issued
Array ( [id] => 12250085 [patent_doc_number] => 09922868 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-20 [patent_title] => 'Integrated circuits using silicon on insulator substrates and methods of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/662427 [patent_app_country] => US [patent_app_date] => 2015-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 5835 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14662427 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/662427
Integrated circuits using silicon on insulator substrates and methods of manufacturing the same Mar 18, 2015 Issued
Array ( [id] => 10309452 [patent_doc_number] => 20150194453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-09 [patent_title] => 'SEMICONDUCTOR STRUCTURE FOR SUPPRESSING HOT CLUSTER' [patent_app_type] => utility [patent_app_number] => 14/662224 [patent_app_country] => US [patent_app_date] => 2015-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2861 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14662224 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/662224
SEMICONDUCTOR STRUCTURE FOR SUPPRESSING HOT CLUSTER Mar 17, 2015 Abandoned
Array ( [id] => 11079397 [patent_doc_number] => 20160276360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-22 [patent_title] => 'HONEYCOMB CELL STRUCTURE THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/660023 [patent_app_country] => US [patent_app_date] => 2015-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 15970 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14660023 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/660023
Honeycomb cell structure three-dimensional non-volatile memory device Mar 16, 2015 Issued
Array ( [id] => 11067438 [patent_doc_number] => 20160264402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-15 [patent_title] => 'STRUCTURE AND METHOD TO MITIGATE SOLDERING OFFSET FOR WAFER-LEVEL CHIP SCALE PACKAGE (WLCSP) APPLICATIONS' [patent_app_type] => utility [patent_app_number] => 14/645650 [patent_app_country] => US [patent_app_date] => 2015-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5217 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14645650 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/645650
Structure and method to mitigate soldering offset for wafer-level chip scale package (WLCSP) applications Mar 11, 2015 Issued
Array ( [id] => 11067439 [patent_doc_number] => 20160264403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-15 [patent_title] => 'SENSOR DEVICE WITH MULTI-STIMULUS SENSING AND METHOD OF FABRICATION' [patent_app_type] => utility [patent_app_number] => 14/656336 [patent_app_country] => US [patent_app_date] => 2015-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7267 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14656336 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/656336
SENSOR DEVICE WITH MULTI-STIMULUS SENSING AND METHOD OF FABRICATION Mar 11, 2015 Abandoned
Array ( [id] => 10809591 [patent_doc_number] => 20160155750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-02 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/642115 [patent_app_country] => US [patent_app_date] => 2015-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6120 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14642115 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/642115
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME Mar 8, 2015 Abandoned
Array ( [id] => 10802852 [patent_doc_number] => 20160149009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/642009 [patent_app_country] => US [patent_app_date] => 2015-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4592 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14642009 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/642009
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Mar 8, 2015 Abandoned
Array ( [id] => 11057183 [patent_doc_number] => 20160254145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-01 [patent_title] => 'METHODS FOR FABRICATING SEMICONDUCTOR STRUCTURE WITH CONDENSED SILICON GERMANIUM LAYER' [patent_app_type] => utility [patent_app_number] => 14/633246 [patent_app_country] => US [patent_app_date] => 2015-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4872 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14633246 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/633246
METHODS FOR FABRICATING SEMICONDUCTOR STRUCTURE WITH CONDENSED SILICON GERMANIUM LAYER Feb 26, 2015 Abandoned
Array ( [id] => 11057218 [patent_doc_number] => 20160254180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-01 [patent_title] => 'SELF ALIGNED RAISED FIN TIP END STI TO IMPROVE THE FIN END EPI QUALITY' [patent_app_type] => utility [patent_app_number] => 14/633341 [patent_app_country] => US [patent_app_date] => 2015-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5436 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14633341 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/633341
SELF ALIGNED RAISED FIN TIP END STI TO IMPROVE THE FIN END EPI QUALITY Feb 26, 2015 Abandoned
Array ( [id] => 13019211 [patent_doc_number] => 10032725 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-24 [patent_title] => Semiconductor structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 14/632371 [patent_app_country] => US [patent_app_date] => 2015-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 7825 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14632371 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/632371
Semiconductor structure and manufacturing method thereof Feb 25, 2015 Issued
Array ( [id] => 11057389 [patent_doc_number] => 20160254351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-01 [patent_title] => 'LDD-FREE SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME' [patent_app_type] => utility [patent_app_number] => 14/632465 [patent_app_country] => US [patent_app_date] => 2015-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6194 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14632465 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/632465
LDD-free semiconductor structure and manufacturing method of the same Feb 25, 2015 Issued
Array ( [id] => 11057278 [patent_doc_number] => 20160254240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-01 [patent_title] => 'Interconnect Structures, Packaged Semiconductor Devices, and Methods of Packaging Semiconductor Devices' [patent_app_type] => utility [patent_app_number] => 14/632858 [patent_app_country] => US [patent_app_date] => 2015-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9729 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14632858 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/632858
Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices Feb 25, 2015 Issued
Array ( [id] => 10740655 [patent_doc_number] => 20160086805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-24 [patent_title] => 'METAL-GATE WITH AN AMORPHOUS METAL LAYER' [patent_app_type] => utility [patent_app_number] => 14/626293 [patent_app_country] => US [patent_app_date] => 2015-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9075 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14626293 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/626293
METAL-GATE WITH AN AMORPHOUS METAL LAYER Feb 18, 2015 Abandoned
Array ( [id] => 10687204 [patent_doc_number] => 20160033349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-04 [patent_title] => 'PRESSURE SENSOR HAVING CAP-DEFINED MEMBRANE' [patent_app_type] => utility [patent_app_number] => 14/622576 [patent_app_country] => US [patent_app_date] => 2015-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 8214 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14622576 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/622576
PRESSURE SENSOR HAVING CAP-DEFINED MEMBRANE Feb 12, 2015 Abandoned
Array ( [id] => 18658799 [patent_doc_number] => 20230304797 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2023-09-28 [patent_title] => MEMS MOTION SENSOR AND METHOD OF MANUFACTURING [patent_app_type] => utility [patent_app_number] => 14/622548 [patent_app_country] => US [patent_app_date] => 2015-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10560 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14622548 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/622548
MEMS motion sensor and method of manufacturing Feb 12, 2015 Issued
Array ( [id] => 18658799 [patent_doc_number] => 20230304797 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2023-09-28 [patent_title] => MEMS MOTION SENSOR AND METHOD OF MANUFACTURING [patent_app_type] => utility [patent_app_number] => 14/622548 [patent_app_country] => US [patent_app_date] => 2015-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10560 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14622548 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/622548
MEMS motion sensor and method of manufacturing Feb 12, 2015 Issued
Array ( [id] => 11043723 [patent_doc_number] => 20160240679 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'SUPPERLATTICE BUFFER STRUCTURE FOR GALLIUM NITRIDE TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 14/620399 [patent_app_country] => US [patent_app_date] => 2015-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8486 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14620399 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/620399
Superlattice buffer structure for gallium nitride transistors Feb 11, 2015 Issued
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