George D Kirschbaum
Examiner (ID: 9114, Phone: (571)272-4232 , Office: P/2913 )
Most Active Art Unit | 2913 |
Art Unit(s) | 2922, 2913 |
Total Applications | 3474 |
Issued Applications | 3317 |
Pending Applications | 8 |
Abandoned Applications | 148 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 4590834
[patent_doc_number] => 07827349
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-11-02
[patent_title] => 'Method and apparatus for coalesced multi-block read'
[patent_app_type] => utility
[patent_app_number] => 12/476156
[patent_app_country] => US
[patent_app_date] => 2009-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 11222
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/827/07827349.pdf
[firstpage_image] =>[orig_patent_app_number] => 12476156
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/476156 | Method and apparatus for coalesced multi-block read | May 31, 2009 | Issued |
Array
(
[id] => 6413151
[patent_doc_number] => 20100306451
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-12-02
[patent_title] => 'ARCHITECTURE FOR NAND FLASH CONSTRAINT ENFORCEMENT'
[patent_app_type] => utility
[patent_app_number] => 12/475710
[patent_app_country] => US
[patent_app_date] => 2009-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4765
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0306/20100306451.pdf
[firstpage_image] =>[orig_patent_app_number] => 12475710
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/475710 | ARCHITECTURE FOR NAND FLASH CONSTRAINT ENFORCEMENT | May 31, 2009 | Abandoned |
Array
(
[id] => 6312478
[patent_doc_number] => 20100070707
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-03-18
[patent_title] => 'PORTABLE ELECTRONIC DEVICE AND DATA PROCESSING METHOD IN PORTABLE ELECTRONIC DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/404506
[patent_app_country] => US
[patent_app_date] => 2009-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 13680
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0070/20100070707.pdf
[firstpage_image] =>[orig_patent_app_number] => 12404506
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/404506 | PORTABLE ELECTRONIC DEVICE AND DATA PROCESSING METHOD IN PORTABLE ELECTRONIC DEVICE | Mar 15, 2009 | Abandoned |
Array
(
[id] => 8912354
[patent_doc_number] => 08484430
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-07-09
[patent_title] => 'Memory system and host device'
[patent_app_type] => utility
[patent_app_number] => 12/403815
[patent_app_country] => US
[patent_app_date] => 2009-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 40
[patent_no_of_words] => 20213
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 272
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12403815
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/403815 | Memory system and host device | Mar 12, 2009 | Issued |
Array
(
[id] => 9555569
[patent_doc_number] => 08762641
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-06-24
[patent_title] => 'Method for achieving power savings by disabling a valid array'
[patent_app_type] => utility
[patent_app_number] => 12/403021
[patent_app_country] => US
[patent_app_date] => 2009-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3731
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 319
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12403021
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/403021 | Method for achieving power savings by disabling a valid array | Mar 11, 2009 | Issued |
Array
(
[id] => 8308620
[patent_doc_number] => 08230173
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-07-24
[patent_title] => 'Cache memory system, data processing apparatus, and storage apparatus'
[patent_app_type] => utility
[patent_app_number] => 12/402114
[patent_app_country] => US
[patent_app_date] => 2009-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3729
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12402114
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/402114 | Cache memory system, data processing apparatus, and storage apparatus | Mar 10, 2009 | Issued |
Array
(
[id] => 5535222
[patent_doc_number] => 20090235010
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-09-17
[patent_title] => 'DATA PROCESSING CIRCUIT, CACHE SYSTEM, AND DATA TRANSFER APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 12/400333
[patent_app_country] => US
[patent_app_date] => 2009-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 8912
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0235/20090235010.pdf
[firstpage_image] =>[orig_patent_app_number] => 12400333
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/400333 | DATA PROCESSING CIRCUIT, CACHE SYSTEM, AND DATA TRANSFER APPARATUS | Mar 8, 2009 | Abandoned |
Array
(
[id] => 6651471
[patent_doc_number] => 20100228944
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-09-09
[patent_title] => 'Apparatus and Method to Translate Virtual Addresses to Physical Addresses in a Base Plus Offset Addressing Mode'
[patent_app_type] => utility
[patent_app_number] => 12/397438
[patent_app_country] => US
[patent_app_date] => 2009-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7167
[patent_no_of_claims] => 47
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0228/20100228944.pdf
[firstpage_image] =>[orig_patent_app_number] => 12397438
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/397438 | Apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing mode | Mar 3, 2009 | Issued |
Array
(
[id] => 8655391
[patent_doc_number] => 08375158
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-02-12
[patent_title] => 'Memory system and block merge method'
[patent_app_type] => utility
[patent_app_number] => 12/396004
[patent_app_country] => US
[patent_app_date] => 2009-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 6194
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12396004
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/396004 | Memory system and block merge method | Mar 1, 2009 | Issued |
Array
(
[id] => 8775358
[patent_doc_number] => 08429333
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-04-23
[patent_title] => 'Memory system with efficient data search processing'
[patent_app_type] => utility
[patent_app_number] => 12/394582
[patent_app_country] => US
[patent_app_date] => 2009-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 24
[patent_no_of_words] => 20339
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12394582
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/394582 | Memory system with efficient data search processing | Feb 26, 2009 | Issued |
Array
(
[id] => 5548079
[patent_doc_number] => 20090157956
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-06-18
[patent_title] => 'SYSTEM AND METHOD FOR MANAGING DISK SPACE IN A THIN-PROVISIONED STORAGE SUBSYSTEM'
[patent_app_type] => utility
[patent_app_number] => 12/393481
[patent_app_country] => US
[patent_app_date] => 2009-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 9098
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0157/20090157956.pdf
[firstpage_image] =>[orig_patent_app_number] => 12393481
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/393481 | System and method for managing disk space in a thin-provisioned storage subsystem | Feb 25, 2009 | Issued |
Array
(
[id] => 5516675
[patent_doc_number] => 20090216982
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-08-27
[patent_title] => 'SELF-LOCKING MASS STORAGE SYSTEM AND METHOD OF OPERATION THEREOF'
[patent_app_type] => utility
[patent_app_number] => 12/392748
[patent_app_country] => US
[patent_app_date] => 2009-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1905
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0216/20090216982.pdf
[firstpage_image] =>[orig_patent_app_number] => 12392748
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/392748 | Self-locking mass storage system and method of operation thereof | Feb 24, 2009 | Issued |
Array
(
[id] => 5491786
[patent_doc_number] => 20090292857
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-11-26
[patent_title] => 'CACHE MEMORY UNIT'
[patent_app_type] => utility
[patent_app_number] => 12/390599
[patent_app_country] => US
[patent_app_date] => 2009-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4422
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0292/20090292857.pdf
[firstpage_image] =>[orig_patent_app_number] => 12390599
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/390599 | CACHE MEMORY UNIT | Feb 22, 2009 | Abandoned |
Array
(
[id] => 6523254
[patent_doc_number] => 20100211744
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-08-19
[patent_title] => 'METHODS AND APARATUS FOR LOW INTRUSION SNOOP INVALIDATION'
[patent_app_type] => utility
[patent_app_number] => 12/388545
[patent_app_country] => US
[patent_app_date] => 2009-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5445
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0211/20100211744.pdf
[firstpage_image] =>[orig_patent_app_number] => 12388545
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/388545 | Methods and apparatus for low intrusion snoop invalidation | Feb 18, 2009 | Issued |
Array
(
[id] => 5305661
[patent_doc_number] => 20090300313
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-12-03
[patent_title] => 'MEMORY CLEARING APPARATUS FOR ZERO CLEARING'
[patent_app_type] => utility
[patent_app_number] => 12/371844
[patent_app_country] => US
[patent_app_date] => 2009-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3117
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0300/20090300313.pdf
[firstpage_image] =>[orig_patent_app_number] => 12371844
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/371844 | MEMORY CLEARING APPARATUS FOR ZERO CLEARING | Feb 15, 2009 | Abandoned |
Array
(
[id] => 5393303
[patent_doc_number] => 20090210616
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-08-20
[patent_title] => 'MEMORY MODULES FOR TWO-DIMENSIONAL MAIN MEMORY'
[patent_app_type] => utility
[patent_app_number] => 12/369725
[patent_app_country] => US
[patent_app_date] => 2009-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 14419
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0210/20090210616.pdf
[firstpage_image] =>[orig_patent_app_number] => 12369725
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/369725 | Memory modules for two-dimensional main memory | Feb 10, 2009 | Issued |
Array
(
[id] => 9458475
[patent_doc_number] => 08719499
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-05-06
[patent_title] => 'Cache-line based notification'
[patent_app_type] => utility
[patent_app_number] => 12/368350
[patent_app_country] => US
[patent_app_date] => 2009-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 5083
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12368350
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/368350 | Cache-line based notification | Feb 9, 2009 | Issued |
Array
(
[id] => 5387412
[patent_doc_number] => 20090228657
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-09-10
[patent_title] => 'Apparatus, processor, cache memory and method of processing vector data'
[patent_app_type] => utility
[patent_app_number] => 12/320888
[patent_app_country] => US
[patent_app_date] => 2009-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5284
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0228/20090228657.pdf
[firstpage_image] =>[orig_patent_app_number] => 12320888
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/320888 | Apparatus, processor, cache memory and method of processing vector data | Feb 5, 2009 | Issued |
Array
(
[id] => 8219961
[patent_doc_number] => 08195873
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-06-05
[patent_title] => 'Ternary content-addressable memory'
[patent_app_type] => utility
[patent_app_number] => 12/322794
[patent_app_country] => US
[patent_app_date] => 2009-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 13
[patent_no_of_words] => 7412
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/195/08195873.pdf
[firstpage_image] =>[orig_patent_app_number] => 12322794
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/322794 | Ternary content-addressable memory | Feb 5, 2009 | Issued |
Array
(
[id] => 6554123
[patent_doc_number] => 20100205377
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-08-12
[patent_title] => 'DEBUG CONTROL FOR SNOOP OPERATIONS IN A MULTIPROCESSOR SYSTEM AND METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 12/366985
[patent_app_country] => US
[patent_app_date] => 2009-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 11691
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0205/20100205377.pdf
[firstpage_image] =>[orig_patent_app_number] => 12366985
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/366985 | Debug control for snoop operations in a multiprocessor system and method thereof | Feb 5, 2009 | Issued |