George D Kirschbaum

Array ( [id] => 19182549 [patent_doc_number] => 11989137 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-21 [patent_title] => Logging cache line lifetime hints when recording bit-accurate trace [patent_app_type] => utility [patent_app_number] => 18/548320 [patent_app_country] => US [patent_app_date] => 2022-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 16671 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18548320 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18345689 [patent_doc_number] => 20230133799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => SEMICONDUCTOR DEVICES AND METHODS FOR PERFORMING PROGRAMMING OPERATIONS [patent_app_type] => utility [patent_app_number] => 17/696638 [patent_app_country] => US [patent_app_date] => 2022-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12778 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17696638 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18267780 [patent_doc_number] => 20230089022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => MEMORY SYSTEM AND METHOD [patent_app_type] => utility [patent_app_number] => 17/689907 [patent_app_country] => US [patent_app_date] => 2022-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10938 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17689907 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18577652 [patent_doc_number] => 11734184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => Effective avoidance of line cache misses [patent_app_type] => utility [patent_app_number] => 17/687103 [patent_app_country] => US [patent_app_date] => 2022-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 7404 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17687103 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19136829 [patent_doc_number] => 11971786 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Backup processing method and server [patent_app_type] => utility [patent_app_number] => 17/678258 [patent_app_country] => US [patent_app_date] => 2022-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 30459 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17678258 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18430483 [patent_doc_number] => 11675702 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-06-13 [patent_title] => Replacement policy information for training table used by prefetch circuitry [patent_app_type] => utility [patent_app_number] => 17/673301 [patent_app_country] => US [patent_app_date] => 2022-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 5 [patent_no_of_words] => 14959 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 351 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17673301 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17736530 [patent_doc_number] => 20220221989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => MEMORY SYSTEM WITH THREADED TRANSACTION SUPPORT [patent_app_type] => utility [patent_app_number] => 17/586575 [patent_app_country] => US [patent_app_date] => 2022-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4740 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17586575 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18531905 [patent_doc_number] => 20230236977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => SELECTABLE CACHE POLICY [patent_app_type] => utility [patent_app_number] => 17/581801 [patent_app_country] => US [patent_app_date] => 2022-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 78933 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17581801 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19045200 [patent_doc_number] => 11934310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Zero bits in L3 tags [patent_app_type] => utility [patent_app_number] => 17/581162 [patent_app_country] => US [patent_app_date] => 2022-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 7041 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17581162 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18519722 [patent_doc_number] => 11709613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-25 [patent_title] => Data migration for memory operation [patent_app_type] => utility [patent_app_number] => 17/580305 [patent_app_country] => US [patent_app_date] => 2022-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 22431 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17580305 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18826517 [patent_doc_number] => 11841793 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-12 [patent_title] => Switch-based free memory tracking in data center environments [patent_app_type] => utility [patent_app_number] => 17/580427 [patent_app_country] => US [patent_app_date] => 2022-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 11241 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17580427 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18547146 [patent_doc_number] => 11720498 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Arithmetic processing device and arithmetic processing method [patent_app_type] => utility [patent_app_number] => 17/573667 [patent_app_country] => US [patent_app_date] => 2022-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 10165 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17573667 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19078096 [patent_doc_number] => 11947461 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Prefetch unit filter for microprocessor [patent_app_type] => utility [patent_app_number] => 17/572245 [patent_app_country] => US [patent_app_date] => 2022-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 10283 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17572245 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18262158 [patent_doc_number] => 11609860 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-03-21 [patent_title] => Techniques for generating a system cache partitioning policy [patent_app_type] => utility [patent_app_number] => 17/557511 [patent_app_country] => US [patent_app_date] => 2021-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 8551 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17557511 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18547139 [patent_doc_number] => 11720491 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => System and method for sharing a cache line between non-contiguous memory areas [patent_app_type] => utility [patent_app_number] => 17/553931 [patent_app_country] => US [patent_app_date] => 2021-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13182 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17553931 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18838991 [patent_doc_number] => 11847062 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Re-fetching data for L3 cache data evictions into a last-level cache [patent_app_type] => utility [patent_app_number] => 17/552703 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5142 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17552703 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18438435 [patent_doc_number] => 20230185730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => TLB ACCESS MONITORING [patent_app_type] => utility [patent_app_number] => 17/548948 [patent_app_country] => US [patent_app_date] => 2021-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7286 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17548948 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18622453 [patent_doc_number] => 11755496 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-09-12 [patent_title] => Memory de-duplication using physical memory aliases [patent_app_type] => utility [patent_app_number] => 17/547888 [patent_app_country] => US [patent_app_date] => 2021-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9027 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17547888 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17484155 [patent_doc_number] => 20220091659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => STATIC POWER REDUCTION IN CACHES USING DETERMINISTIC NAPS [patent_app_type] => utility [patent_app_number] => 17/541776 [patent_app_country] => US [patent_app_date] => 2021-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4575 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17541776 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18248146 [patent_doc_number] => 11604735 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-03-14 [patent_title] => Host memory buffer (HMB) random cache access [patent_app_type] => utility [patent_app_number] => 17/541028 [patent_app_country] => US [patent_app_date] => 2021-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 18339 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17541028 [rel_patent_id] =>[rel_patent_doc_number] =>)