![](/images/general/no_picture/200_user.png)
George D Kirschbaum
Examiner (ID: 9114, Phone: (571)272-4232 , Office: P/2913 )
Most Active Art Unit | 2913 |
Art Unit(s) | 2922, 2913 |
Total Applications | 3474 |
Issued Applications | 3317 |
Pending Applications | 8 |
Abandoned Applications | 148 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 17128710
[patent_doc_number] => 20210303479
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-09-30
[patent_title] => APPARATUS AND METHOD
[patent_app_type] => utility
[patent_app_number] => 16/834171
[patent_app_country] => US
[patent_app_date] => 2020-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7905
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 186
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16834171
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/834171 | Apparatus and method for processing address translation and invalidation transactions | Mar 29, 2020 | Issued |
Array
(
[id] => 17194942
[patent_doc_number] => 11163699
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-11-02
[patent_title] => Managing least recently used cache using reduced memory footprint sequence container
[patent_app_type] => utility
[patent_app_number] => 16/834363
[patent_app_country] => US
[patent_app_date] => 2020-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 10142
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 211
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16834363
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/834363 | Managing least recently used cache using reduced memory footprint sequence container | Mar 29, 2020 | Issued |
Array
(
[id] => 16179129
[patent_doc_number] => 20200226097
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-16
[patent_title] => SAND TIMER ALGORITHM FOR TRACKING IN-FLIGHT DATA STORAGE REQUESTS FOR DATA REPLICATION
[patent_app_type] => utility
[patent_app_number] => 16/832202
[patent_app_country] => US
[patent_app_date] => 2020-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11208
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16832202
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/832202 | Sand timer algorithm for tracking in-flight data storage requests for data replication | Mar 26, 2020 | Issued |
Array
(
[id] => 17283146
[patent_doc_number] => 11200175
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-12-14
[patent_title] => Memory accessor invailidation
[patent_app_type] => utility
[patent_app_number] => 16/825021
[patent_app_country] => US
[patent_app_date] => 2020-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 9805
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16825021
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/825021 | Memory accessor invailidation | Mar 19, 2020 | Issued |
Array
(
[id] => 16285328
[patent_doc_number] => 20200278930
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-09-03
[patent_title] => DISTRIBUTED COHERENCE DIRECTORY SUBSYSTEM WITH EXCLUSIVE DATA REGIONS
[patent_app_type] => utility
[patent_app_number] => 16/821632
[patent_app_country] => US
[patent_app_date] => 2020-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7002
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16821632
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/821632 | Distributed coherence directory subsystem with exclusive data regions | Mar 16, 2020 | Issued |
Array
(
[id] => 17613915
[patent_doc_number] => 20220156195
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-19
[patent_title] => Snoop filter device
[patent_app_type] => utility
[patent_app_number] => 17/440128
[patent_app_country] => US
[patent_app_date] => 2020-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5595
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17440128
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/440128 | Snoop filter device | Mar 12, 2020 | Issued |
Array
(
[id] => 16255408
[patent_doc_number] => 20200264782
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-08-20
[patent_title] => MEMORY SYSTEM WITH THREADED TRANSACTION SUPPORT
[patent_app_type] => utility
[patent_app_number] => 16/805535
[patent_app_country] => US
[patent_app_date] => 2020-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4713
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16805535
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/805535 | Memory system with threaded transaction support | Feb 27, 2020 | Issued |
Array
(
[id] => 17528701
[patent_doc_number] => 11301389
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-04-12
[patent_title] => Executable memory page validation system and method
[patent_app_type] => utility
[patent_app_number] => 17/434763
[patent_app_country] => US
[patent_app_date] => 2020-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5018
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17434763
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/434763 | Executable memory page validation system and method | Feb 26, 2020 | Issued |
Array
(
[id] => 18189442
[patent_doc_number] => 11580027
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-02-14
[patent_title] => Multi-tile memory management mechanism
[patent_app_type] => utility
[patent_app_number] => 16/802427
[patent_app_country] => US
[patent_app_date] => 2020-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 34
[patent_figures_cnt] => 41
[patent_no_of_words] => 25244
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16802427
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/802427 | Multi-tile memory management mechanism | Feb 25, 2020 | Issued |
Array
(
[id] => 17054428
[patent_doc_number] => 20210263862
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-08-26
[patent_title] => MAINTAINING GHOST CACHE STATISTICS FOR DEMOTED DATA ELEMENTS
[patent_app_type] => utility
[patent_app_number] => 16/798330
[patent_app_country] => US
[patent_app_date] => 2020-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11431
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16798330
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/798330 | Maintaining ghost cache statistics for demoted data elements | Feb 21, 2020 | Issued |
Array
(
[id] => 15998103
[patent_doc_number] => 20200174922
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-04
[patent_title] => RESOURCE RECLAMATION METHOD AND APPARATUS
[patent_app_type] => utility
[patent_app_number] => 16/784109
[patent_app_country] => US
[patent_app_date] => 2020-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10156
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 30
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16784109
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/784109 | RESOURCE RECLAMATION METHOD AND APPARATUS | Feb 5, 2020 | Abandoned |
Array
(
[id] => 16270860
[patent_doc_number] => 20200272347
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-08-27
[patent_title] => MACHINE LEARNING-BASED DATA OBJECT STORAGE
[patent_app_type] => utility
[patent_app_number] => 16/776292
[patent_app_country] => US
[patent_app_date] => 2020-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 44083
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16776292
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/776292 | Machine learning-based data object storage | Jan 28, 2020 | Issued |
Array
(
[id] => 17076576
[patent_doc_number] => 11112974
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-09-07
[patent_title] => Dynamic cache management in storage devices
[patent_app_type] => utility
[patent_app_number] => 16/774746
[patent_app_country] => US
[patent_app_date] => 2020-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 10672
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16774746
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/774746 | Dynamic cache management in storage devices | Jan 27, 2020 | Issued |
Array
(
[id] => 16644146
[patent_doc_number] => 10922002
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-02-16
[patent_title] => Processing I/O requests using a redundant array of independent disks (RAID)
[patent_app_type] => utility
[patent_app_number] => 16/750166
[patent_app_country] => US
[patent_app_date] => 2020-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 6937
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16750166
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/750166 | Processing I/O requests using a redundant array of independent disks (RAID) | Jan 22, 2020 | Issued |
Array
(
[id] => 17817328
[patent_doc_number] => 11422941
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-08-23
[patent_title] => Calculating the optimal number of LBNs to prefetch per CPU
[patent_app_type] => utility
[patent_app_number] => 16/748790
[patent_app_country] => US
[patent_app_date] => 2020-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 4077
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16748790
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/748790 | Calculating the optimal number of LBNs to prefetch per CPU | Jan 20, 2020 | Issued |
Array
(
[id] => 17394878
[patent_doc_number] => 11243892
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-02-08
[patent_title] => Partitioning TLB or cache allocation
[patent_app_type] => utility
[patent_app_number] => 16/745019
[patent_app_country] => US
[patent_app_date] => 2020-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 20
[patent_no_of_words] => 20771
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16745019
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/745019 | Partitioning TLB or cache allocation | Jan 15, 2020 | Issued |
Array
(
[id] => 17499492
[patent_doc_number] => 11288198
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-03-29
[patent_title] => Effective avoidance of line cache misses
[patent_app_type] => utility
[patent_app_number] => 15/733358
[patent_app_country] => US
[patent_app_date] => 2019-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 7356
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15733358
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/733358 | Effective avoidance of line cache misses | Dec 22, 2019 | Issued |
Array
(
[id] => 18030784
[patent_doc_number] => 11513973
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-11-29
[patent_title] => Arbitration scheme for coherent and non-coherent memory requests
[patent_app_type] => utility
[patent_app_number] => 16/723185
[patent_app_country] => US
[patent_app_date] => 2019-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 8600
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16723185
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/723185 | Arbitration scheme for coherent and non-coherent memory requests | Dec 19, 2019 | Issued |
Array
(
[id] => 16737512
[patent_doc_number] => 10963164
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-30
[patent_title] => Non-deterministic memory protocol
[patent_app_type] => utility
[patent_app_number] => 16/723589
[patent_app_country] => US
[patent_app_date] => 2019-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7120
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16723589
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/723589 | Non-deterministic memory protocol | Dec 19, 2019 | Issued |
Array
(
[id] => 16077643
[patent_doc_number] => 20200192808
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-18
[patent_title] => METHOD FOR IMPLEMENTING A VIRTUAL ADDRESS SPACE ON AN EMBEDDED SYSTEM
[patent_app_type] => utility
[patent_app_number] => 16/716619
[patent_app_country] => US
[patent_app_date] => 2019-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4023
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -5
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16716619
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/716619 | Method for implementing a virtual address space on an embedded system | Dec 16, 2019 | Issued |