Search

George G King

Examiner (ID: 5136, Phone: (303)297-4273 , Office: P/2872 )

Most Active Art Unit
2872
Art Unit(s)
2872
Total Applications
604
Issued Applications
316
Pending Applications
88
Abandoned Applications
200

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18189607 [patent_doc_number] => 11580195 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-02-14 [patent_title] => Quantum modulation-based data compression [patent_app_type] => utility [patent_app_number] => 16/827352 [patent_app_country] => US [patent_app_date] => 2020-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 8786 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16827352 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/827352
Quantum modulation-based data compression Mar 22, 2020 Issued
Array ( [id] => 16164849 [patent_doc_number] => 20200220657 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-09 [patent_title] => INFORMATION PROCESSING METHOD, DEVICE, AND COMMUNICATIONS SYSTEM [patent_app_type] => utility [patent_app_number] => 16/821986 [patent_app_country] => US [patent_app_date] => 2020-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12578 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16821986 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/821986
Information processing method, device, and communications system Mar 16, 2020 Issued
Array ( [id] => 18263647 [patent_doc_number] => 11611358 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-21 [patent_title] => Systems and methods for detecting or preventing false detection of three error bits by SEC [patent_app_type] => utility [patent_app_number] => 16/816093 [patent_app_country] => US [patent_app_date] => 2020-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7235 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16816093 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/816093
Systems and methods for detecting or preventing false detection of three error bits by SEC Mar 10, 2020 Issued
Array ( [id] => 17086476 [patent_doc_number] => 20210281483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => NOISE GENERATION FOR DIFFERENTIAL PRIVACY [patent_app_type] => utility [patent_app_number] => 16/809900 [patent_app_country] => US [patent_app_date] => 2020-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11392 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16809900 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/809900
Noise generation for differential privacy Mar 4, 2020 Issued
Array ( [id] => 17019057 [patent_doc_number] => 11088710 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-10 [patent_title] => Memory controllers and memory systems including the same [patent_app_type] => utility [patent_app_number] => 16/809949 [patent_app_country] => US [patent_app_date] => 2020-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 9915 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16809949 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/809949
Memory controllers and memory systems including the same Mar 4, 2020 Issued
Array ( [id] => 17439672 [patent_doc_number] => 11265017 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Modulator and modulation method using non-uniform 16-symbol signal constellation for low-density parity check codeword having 4/15 code rate [patent_app_type] => utility [patent_app_number] => 16/808288 [patent_app_country] => US [patent_app_date] => 2020-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7975 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16808288 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/808288
Modulator and modulation method using non-uniform 16-symbol signal constellation for low-density parity check codeword having 4/15 code rate Mar 2, 2020 Issued
Array ( [id] => 17180381 [patent_doc_number] => 11157625 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-26 [patent_title] => Verifying basic input/output system (BIOS) boot block code [patent_app_type] => utility [patent_app_number] => 16/806627 [patent_app_country] => US [patent_app_date] => 2020-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3337 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16806627 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/806627
Verifying basic input/output system (BIOS) boot block code Mar 1, 2020 Issued
Array ( [id] => 16866521 [patent_doc_number] => 11025281 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-01 [patent_title] => Memory system [patent_app_type] => utility [patent_app_number] => 16/806322 [patent_app_country] => US [patent_app_date] => 2020-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7850 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16806322 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/806322
Memory system Mar 1, 2020 Issued
Array ( [id] => 16959727 [patent_doc_number] => 11063612 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-07-13 [patent_title] => Parallelizing encoding of binary symmetry-invariant product codes [patent_app_type] => utility [patent_app_number] => 16/806387 [patent_app_country] => US [patent_app_date] => 2020-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 32 [patent_no_of_words] => 13485 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16806387 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/806387
Parallelizing encoding of binary symmetry-invariant product codes Mar 1, 2020 Issued
Array ( [id] => 16255569 [patent_doc_number] => 20200264943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-20 [patent_title] => Memory Controller With Error Detection And Retry Modes Of Operation [patent_app_type] => utility [patent_app_number] => 16/805619 [patent_app_country] => US [patent_app_date] => 2020-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11772 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16805619 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/805619
Memory controller with error detection and retry modes of operation Feb 27, 2020 Issued
Array ( [id] => 16082585 [patent_doc_number] => 20200195279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => Device and Method for Generating a Multi-Kernel Polar Code [patent_app_type] => utility [patent_app_number] => 16/797214 [patent_app_country] => US [patent_app_date] => 2020-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7068 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16797214 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/797214
Device and method for generating a multi-kernel polar code Feb 20, 2020 Issued
Array ( [id] => 18624411 [patent_doc_number] => 11757473 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Telecommunications method [patent_app_type] => utility [patent_app_number] => 17/430808 [patent_app_country] => US [patent_app_date] => 2020-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6715 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17430808 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/430808
Telecommunications method Feb 12, 2020 Issued
Array ( [id] => 17017077 [patent_doc_number] => 11086716 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-10 [patent_title] => Memory controller and method for decoding memory devices with early hard-decode exit [patent_app_type] => utility [patent_app_number] => 16/790547 [patent_app_country] => US [patent_app_date] => 2020-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7642 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16790547 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/790547
Memory controller and method for decoding memory devices with early hard-decode exit Feb 12, 2020 Issued
Array ( [id] => 17033596 [patent_doc_number] => 11095420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Preemption indicator techniques [patent_app_type] => utility [patent_app_number] => 16/789797 [patent_app_country] => US [patent_app_date] => 2020-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 25 [patent_no_of_words] => 15547 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16789797 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/789797
Preemption indicator techniques Feb 12, 2020 Issued
Array ( [id] => 16160725 [patent_doc_number] => 20200218595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-09 [patent_title] => METHOD AND ARCHITECTURE FOR CRITICAL SYSTEMS UTILIZING MULTI-CENTRIC ORTHOGONAL TOPOLOGY AND PERVASIVE RULES-DRIVEN DATA AND CONTROL ENCODING [patent_app_type] => utility [patent_app_number] => 16/787266 [patent_app_country] => US [patent_app_date] => 2020-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16533 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16787266 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/787266
METHOD AND ARCHITECTURE FOR CRITICAL SYSTEMS UTILIZING MULTI-CENTRIC ORTHOGONAL TOPOLOGY AND PERVASIVE RULES-DRIVEN DATA AND CONTROL ENCODING Feb 10, 2020 Abandoned
Array ( [id] => 16002661 [patent_doc_number] => 20200177201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => SYSTEM AND METHOD FOR PROCESSING POLAR CODE [patent_app_type] => utility [patent_app_number] => 16/784050 [patent_app_country] => US [patent_app_date] => 2020-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8770 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16784050 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/784050
System and method for processing polar code Feb 5, 2020 Issued
Array ( [id] => 16820656 [patent_doc_number] => 11005502 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Iterative decoding circuit and decoding method [patent_app_type] => utility [patent_app_number] => 16/780919 [patent_app_country] => US [patent_app_date] => 2020-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2649 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16780919 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/780919
Iterative decoding circuit and decoding method Feb 3, 2020 Issued
Array ( [id] => 17819138 [patent_doc_number] => 11424766 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-08-23 [patent_title] => Method and device for energy-efficient decoders [patent_app_type] => utility [patent_app_number] => 16/778918 [patent_app_country] => US [patent_app_date] => 2020-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 7145 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16778918 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/778918
Method and device for energy-efficient decoders Jan 30, 2020 Issued
Array ( [id] => 17605925 [patent_doc_number] => 11334413 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-17 [patent_title] => Estimating an error rate associated with memory [patent_app_type] => utility [patent_app_number] => 16/752859 [patent_app_country] => US [patent_app_date] => 2020-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6418 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16752859 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/752859
Estimating an error rate associated with memory Jan 26, 2020 Issued
Array ( [id] => 17019060 [patent_doc_number] => 11088713 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-10 [patent_title] => Solid state drive implementing a rate-compatible polar code [patent_app_type] => utility [patent_app_number] => 16/748002 [patent_app_country] => US [patent_app_date] => 2020-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8598 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 360 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16748002 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/748002
Solid state drive implementing a rate-compatible polar code Jan 20, 2020 Issued
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