Search

George Giroux

Examiner (ID: 2484, Phone: (571)272-9769 , Office: P/2182 )

Most Active Art Unit
2183
Art Unit(s)
2125, 2183, 2128, 2182
Total Applications
674
Issued Applications
410
Pending Applications
64
Abandoned Applications
218

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11056324 [patent_doc_number] => 20160253286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-01 [patent_title] => 'PROGRAM PROFILER CIRCUIT, PROCESSOR, AND PROGRAM COUNTING METHOD' [patent_app_type] => utility [patent_app_number] => 14/987087 [patent_app_country] => US [patent_app_date] => 2016-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12073 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14987087 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/987087
PROGRAM PROFILER CIRCUIT, PROCESSOR, AND PROGRAM COUNTING METHOD Jan 3, 2016 Abandoned
Array ( [id] => 11013197 [patent_doc_number] => 20160210150 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-21 [patent_title] => 'ACCELERATED EXECUTION OF TARGET OF EXECUTE INSTRUCTION' [patent_app_type] => utility [patent_app_number] => 14/980476 [patent_app_country] => US [patent_app_date] => 2015-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4858 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14980476 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/980476
Accelerated execution of target of execute instruction Dec 27, 2015 Issued
Array ( [id] => 11651444 [patent_doc_number] => 20170147345 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'MULTIPLE OPERATION INTERFACE TO SHARED COPROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/946054 [patent_app_country] => US [patent_app_date] => 2015-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10652 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14946054 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/946054
MULTIPLE OPERATION INTERFACE TO SHARED COPROCESSOR Nov 18, 2015 Abandoned
Array ( [id] => 14918045 [patent_doc_number] => 10430342 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-01 [patent_title] => Optimizing thread selection at fetch, select, and commit stages of processor core pipeline [patent_app_type] => utility [patent_app_number] => 14/945054 [patent_app_country] => US [patent_app_date] => 2015-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10929 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14945054 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/945054
Optimizing thread selection at fetch, select, and commit stages of processor core pipeline Nov 17, 2015 Issued
Array ( [id] => 10808508 [patent_doc_number] => 20160154666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-02 [patent_title] => 'Efficient Detection and Response to Spin Waits in Multi-Processor Virtual Machines' [patent_app_type] => utility [patent_app_number] => 14/945206 [patent_app_country] => US [patent_app_date] => 2015-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3957 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14945206 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/945206
Efficient detection and response to spin waits in multi-processor virtual machines Nov 17, 2015 Issued
Array ( [id] => 12004229 [patent_doc_number] => 20170308383 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-26 [patent_title] => 'BIT GROUP INTERLEAVE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 15/508157 [patent_app_country] => US [patent_app_date] => 2015-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 27866 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15508157 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/508157
BIT GROUP INTERLEAVE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS Sep 3, 2015 Abandoned
Array ( [id] => 16171477 [patent_doc_number] => 10713044 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-14 [patent_title] => Bit shuffle processors, methods, systems, and instructions [patent_app_type] => utility [patent_app_number] => 15/508284 [patent_app_country] => US [patent_app_date] => 2015-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 32 [patent_no_of_words] => 29298 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15508284 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/508284
Bit shuffle processors, methods, systems, and instructions Sep 3, 2015 Issued
Array ( [id] => 10485289 [patent_doc_number] => 20150370308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-24 [patent_title] => 'BRANCH PREDICTION WITH POWER USAGE PREDICTION AND CONTROL' [patent_app_type] => utility [patent_app_number] => 14/841016 [patent_app_country] => US [patent_app_date] => 2015-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10151 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14841016 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/841016
Branch prediction with power usage prediction and control Aug 30, 2015 Issued
Array ( [id] => 16263384 [patent_doc_number] => 10754818 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-25 [patent_title] => Multiprocessor device for executing vector processing commands [patent_app_type] => utility [patent_app_number] => 15/317183 [patent_app_country] => US [patent_app_date] => 2015-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8645 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15317183 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/317183
Multiprocessor device for executing vector processing commands Aug 4, 2015 Issued
Array ( [id] => 10416573 [patent_doc_number] => 20150301583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-22 [patent_title] => 'PROGRAM AND DATA ANNOTATION FOR HARDWARE CUSTOMIZATION AND ENERGY OPTIMIZATION' [patent_app_type] => utility [patent_app_number] => 14/752787 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6203 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14752787 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/752787
Program and data annotation for hardware customization and energy optimization Jun 25, 2015 Issued
Array ( [id] => 10349652 [patent_doc_number] => 20150234657 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-20 [patent_title] => 'LATEST PRODUCER TRACKING IN AN OUT-OF-ORDER PROCESSOR, AND APPLICATIONS THEREOF' [patent_app_type] => utility [patent_app_number] => 14/704416 [patent_app_country] => US [patent_app_date] => 2015-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7542 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14704416 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/704416
Latest producer tracking in an out-of-order processor, and applications thereof May 4, 2015 Issued
Array ( [id] => 10349654 [patent_doc_number] => 20150234659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-20 [patent_title] => 'APPARATUS AND METHOD FOR ASYMMETRIC DUAL PATH PROCESSING' [patent_app_type] => utility [patent_app_number] => 14/700343 [patent_app_country] => US [patent_app_date] => 2015-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4078 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14700343 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/700343
Apparatus and method for asymmetric dual path processing Apr 29, 2015 Issued
Array ( [id] => 10342385 [patent_doc_number] => 20150227390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-13 [patent_title] => 'IMPLEMENTATION OF MULTI-TASKING ON A DIGITAL SIGNAL PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/697279 [patent_app_country] => US [patent_app_date] => 2015-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3568 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14697279 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/697279
Implementation of multi-tasking on a digital signal processor with a hardware stack Apr 26, 2015 Issued
Array ( [id] => 12114345 [patent_doc_number] => 09870340 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-16 [patent_title] => 'Multithreading in vector processors' [patent_app_type] => utility [patent_app_number] => 14/672568 [patent_app_country] => US [patent_app_date] => 2015-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5905 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 325 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14672568 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/672568
Multithreading in vector processors Mar 29, 2015 Issued
Array ( [id] => 10408757 [patent_doc_number] => 20150293766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-15 [patent_title] => 'PROCESSOR AND METHOD' [patent_app_type] => utility [patent_app_number] => 14/609818 [patent_app_country] => US [patent_app_date] => 2015-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3663 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14609818 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/609818
PROCESSOR AND METHOD Jan 29, 2015 Abandoned
Array ( [id] => 16417055 [patent_doc_number] => 10824953 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Reconfigurable array processor for pattern matching [patent_app_type] => utility [patent_app_number] => 14/602059 [patent_app_country] => US [patent_app_date] => 2015-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 15361 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14602059 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/602059
Reconfigurable array processor for pattern matching Jan 20, 2015 Issued
Array ( [id] => 11013200 [patent_doc_number] => 20160210153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-21 [patent_title] => 'ACCELERATED INSTRUCTION EXECUTION' [patent_app_type] => utility [patent_app_number] => 14/599693 [patent_app_country] => US [patent_app_date] => 2015-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4874 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14599693 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/599693
Accelerated execution of execute instruction target Jan 18, 2015 Issued
Array ( [id] => 10982590 [patent_doc_number] => 20160179534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'INSTRUCTION LENGTH DECODING' [patent_app_type] => utility [patent_app_number] => 14/580603 [patent_app_country] => US [patent_app_date] => 2014-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 21671 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14580603 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/580603
Instruction length decoding Dec 22, 2014 Issued
Array ( [id] => 10982605 [patent_doc_number] => 20160179549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'Instruction and Logic for Loop Stream Detection' [patent_app_type] => utility [patent_app_number] => 14/580498 [patent_app_country] => US [patent_app_date] => 2014-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 22232 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14580498 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/580498
Instruction and Logic for Loop Stream Detection Dec 22, 2014 Abandoned
Array ( [id] => 10982600 [patent_doc_number] => 20160179544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'INSTRUCTION AND LOGIC FOR SUPPRESSION OF HARDWARE PREFETCHERS' [patent_app_type] => utility [patent_app_number] => 14/580999 [patent_app_country] => US [patent_app_date] => 2014-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 21975 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14580999 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/580999
Instruction and logic for suppression of hardware prefetchers Dec 22, 2014 Issued
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