| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3604812
[patent_doc_number] => 05568646
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-22
[patent_title] => 'Multiple instruction set mapping'
[patent_app_type] => 1
[patent_app_number] => 8/308838
[patent_app_country] => US
[patent_app_date] => 1994-09-19
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[firstpage_image] =>[orig_patent_app_number] => 308838
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/308838 | Multiple instruction set mapping | Sep 18, 1994 | Issued |
| 08/308836 | APPARATUS AND METHOD FOR DATA PROCESSING WITH MULTIPLE INSTRUCTION SETS | Sep 18, 1994 | Abandoned |
Array
(
[id] => 3803444
[patent_doc_number] => 05737589
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-07
[patent_title] => 'Data transfer system and method including tuning of a sampling clock used for latching data'
[patent_app_type] => 1
[patent_app_number] => 8/308346
[patent_app_country] => US
[patent_app_date] => 1994-09-19
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[pdf_file] => patents/05/737/05737589.pdf
[firstpage_image] =>[orig_patent_app_number] => 308346
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/308346 | Data transfer system and method including tuning of a sampling clock used for latching data | Sep 18, 1994 | Issued |
Array
(
[id] => 3622108
[patent_doc_number] => 05590358
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-31
[patent_title] => 'Processor with word-aligned branch target in a byte-oriented instruction set'
[patent_app_type] => 1
[patent_app_number] => 8/308337
[patent_app_country] => US
[patent_app_date] => 1994-09-16
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/590/05590358.pdf
[firstpage_image] =>[orig_patent_app_number] => 308337
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/308337 | Processor with word-aligned branch target in a byte-oriented instruction set | Sep 15, 1994 | Issued |
Array
(
[id] => 4215301
[patent_doc_number] => 06014713
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-11
[patent_title] => 'Computer with retractable optical fiber connector assembly having rotatable spool with optical fiber for connecting the computer to external component'
[patent_app_type] => 1
[patent_app_number] => 8/307498
[patent_app_country] => US
[patent_app_date] => 1994-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/06/014/06014713.pdf
[firstpage_image] =>[orig_patent_app_number] => 307498
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/307498 | Computer with retractable optical fiber connector assembly having rotatable spool with optical fiber for connecting the computer to external component | Sep 13, 1994 | Issued |
Array
(
[id] => 1438599
[patent_doc_number] => 06356938
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-03-12
[patent_title] => 'System and method for transmission of information packets between provider and consumer processors'
[patent_app_type] => B1
[patent_app_number] => 08/303809
[patent_app_country] => US
[patent_app_date] => 1994-09-09
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/356/06356938.pdf
[firstpage_image] =>[orig_patent_app_number] => 08303809
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/303809 | System and method for transmission of information packets between provider and consumer processors | Sep 8, 1994 | Issued |
| 08/301480 | COMPUTER-BASED WORKSTATION FOR GENERATION OF LOGIC DIAGRAMS FROM NATURAL LANGUAGE TEXT STRUCTURED BY THE INSERTION OF SCRIPT SYMBOLS | Sep 7, 1994 | Abandoned |
| 08/303080 | SELECTABLE PROCESSING REGISTERS AND METHOD | Sep 7, 1994 | Abandoned |
Array
(
[id] => 3603441
[patent_doc_number] => 05586276
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-17
[patent_title] => 'End bit markers for indicating the end of a variable length instruction to facilitate parallel processing of sequential instructions'
[patent_app_type] => 1
[patent_app_number] => 8/301313
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[pdf_file] => patents/05/586/05586276.pdf
[firstpage_image] =>[orig_patent_app_number] => 301313
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/301313 | End bit markers for indicating the end of a variable length instruction to facilitate parallel processing of sequential instructions | Sep 5, 1994 | Issued |
| 08/300815 | COMPUTER ARCHITECTURE CAPABLE OF CONCURRENT ISSUANCE AND EXECUTION OF GENERAL PURPOSE MULTIPLE INSTRUCTION | Sep 1, 1994 | Abandoned |
Array
(
[id] => 3626037
[patent_doc_number] => 05566342
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-15
[patent_title] => 'Scalable switch wiring technique for large arrays of processors'
[patent_app_type] => 1
[patent_app_number] => 8/298828
[patent_app_country] => US
[patent_app_date] => 1994-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[pdf_file] => patents/05/566/05566342.pdf
[firstpage_image] =>[orig_patent_app_number] => 298828
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/298828 | Scalable switch wiring technique for large arrays of processors | Aug 30, 1994 | Issued |
| 08/297766 | NETWORK SYSTEM HAVING PLURAL MULTIMEDIA SERVERS FOR DIFFERENT TYPES OF DATA | Aug 29, 1994 | Abandoned |
Array
(
[id] => 3524325
[patent_doc_number] => 05564055
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-08
[patent_title] => 'PCMCIA slot expander and method'
[patent_app_type] => 1
[patent_app_number] => 8/298240
[patent_app_country] => US
[patent_app_date] => 1994-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[pdf_file] => patents/05/564/05564055.pdf
[firstpage_image] =>[orig_patent_app_number] => 298240
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/298240 | PCMCIA slot expander and method | Aug 29, 1994 | Issued |
Array
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[id] => 3613098
[patent_doc_number] => 05560033
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-09-24
[patent_title] => 'System for providing automatic power control for highly available n+k processors'
[patent_app_type] => 1
[patent_app_number] => 8/297458
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[pdf_file] => patents/05/560/05560033.pdf
[firstpage_image] =>[orig_patent_app_number] => 297458
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/297458 | System for providing automatic power control for highly available n+k processors | Aug 28, 1994 | Issued |
Array
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[id] => 3750663
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-16
[patent_title] => 'Flow control apparatus and method for a computer interconnect using adaptive credits and flow control tags'
[patent_app_type] => 1
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[firstpage_image] =>[orig_patent_app_number] => 296215
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/296215 | Flow control apparatus and method for a computer interconnect using adaptive credits and flow control tags | Aug 24, 1994 | Issued |
Array
(
[id] => 3622063
[patent_doc_number] => 05590356
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-31
[patent_title] => 'Mesh parallel computer architecture apparatus and associated methods'
[patent_app_type] => 1
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[firstpage_image] =>[orig_patent_app_number] => 294757
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/294757 | Mesh parallel computer architecture apparatus and associated methods | Aug 22, 1994 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/294490 | Broadband communications network services access platform | Aug 22, 1994 | Issued |
Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/287919 | Data driven processor, a data driven information processing device, and a method of verifying path connections of a plurality of data driven processors in such a data driven information processing device | Aug 8, 1994 | Issued |