| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3487484
[patent_doc_number] => 05428809
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-06-27
[patent_title] => 'High speed parallel microcode program controller with high efficiency instruction set for ASIC'
[patent_app_type] => 1
[patent_app_number] => 8/220403
[patent_app_country] => US
[patent_app_date] => 1994-03-29
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 220403
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/220403 | High speed parallel microcode program controller with high efficiency instruction set for ASIC | Mar 28, 1994 | Issued |
| 08/218413 | PROGRAMMABLE HARDWARE COUNTER | Mar 24, 1994 | Abandoned |
| 08/220961 | WRITE ONCE READ ONLY REGISTERS | Mar 24, 1994 | Abandoned |
| 08/217795 | ALTERNATE I/O PORT ACCESS TO STANDARD REGISTER SET | Mar 24, 1994 | Abandoned |
| 08/217646 | APPARATUS TO ALLOW A CPU TO CONTROL THE RELOCATION OF CODE BLOCKS FOR OTHE CPUS | Mar 24, 1994 | Abandoned |
| 08/218273 | METHOD TO STORE PRIVILEGED DATA WITHIN THE PRIMARY CPU MEMORY SPACE | Mar 24, 1994 | Abandoned |
| 08/217328 | APPARATUS AND METHOD FOR COMMUNICATION SWITCHING INCLUDING PROVIDING INFORMATION OVERFLOW INDICATIONS | Mar 23, 1994 | Abandoned |
Array
(
[id] => 3870501
[patent_doc_number] => 05706429
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-06
[patent_title] => 'Transaction processing system and method'
[patent_app_type] => 1
[patent_app_number] => 8/210977
[patent_app_country] => US
[patent_app_date] => 1994-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[pdf_file] => patents/05/706/05706429.pdf
[firstpage_image] =>[orig_patent_app_number] => 210977
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/210977 | Transaction processing system and method | Mar 20, 1994 | Issued |
Array
(
[id] => 3576936
[patent_doc_number] => 05483661
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-01-09
[patent_title] => 'Method of verifying identification data in data driven information processing system'
[patent_app_type] => 1
[patent_app_number] => 8/208477
[patent_app_country] => US
[patent_app_date] => 1994-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 37
[patent_no_of_words] => 9119
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 278
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/483/05483661.pdf
[firstpage_image] =>[orig_patent_app_number] => 208477
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/208477 | Method of verifying identification data in data driven information processing system | Mar 9, 1994 | Issued |
| 08/208500 | ADAPTER FOR INTERFACING A COMPUTER TO A MULTICHANNEL DIGITAL NETWORK, WITH PORT FOR A TELEPHONE | Mar 8, 1994 | Abandoned |
| 08/207155 | SYSTEM INCLUDING PLURALITY OF DATA DRIVEN PROCESSORS CONNECTED TO EACH OTHER | Mar 7, 1994 | Abandoned |
Array
(
[id] => 3589545
[patent_doc_number] => 05524265
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-04
[patent_title] => 'Architecture of transfer processor'
[patent_app_type] => 1
[patent_app_number] => 8/207503
[patent_app_country] => US
[patent_app_date] => 1994-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/524/05524265.pdf
[firstpage_image] =>[orig_patent_app_number] => 207503
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/207503 | Architecture of transfer processor | Mar 7, 1994 | Issued |
Array
(
[id] => 3603017
[patent_doc_number] => 05488729
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-01-30
[patent_title] => 'Central processing unit architecture with symmetric instruction scheduling to achieve multiple instruction launch and execution'
[patent_app_type] => 1
[patent_app_number] => 8/208091
[patent_app_country] => US
[patent_app_date] => 1994-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
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[patent_no_of_words] => 25989
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/488/05488729.pdf
[firstpage_image] =>[orig_patent_app_number] => 208091
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/208091 | Central processing unit architecture with symmetric instruction scheduling to achieve multiple instruction launch and execution | Mar 6, 1994 | Issued |
Array
(
[id] => 3744901
[patent_doc_number] => 05694549
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-02
[patent_title] => 'Multi-provider on-line communications system'
[patent_app_type] => 1
[patent_app_number] => 8/205195
[patent_app_country] => US
[patent_app_date] => 1994-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/694/05694549.pdf
[firstpage_image] =>[orig_patent_app_number] => 205195
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/205195 | Multi-provider on-line communications system | Mar 2, 1994 | Issued |
Array
(
[id] => 3502035
[patent_doc_number] => 05471633
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-28
[patent_title] => 'Idiom recognizer within a register alias table'
[patent_app_type] => 1
[patent_app_number] => 8/205842
[patent_app_country] => US
[patent_app_date] => 1994-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
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[patent_no_of_words] => 33672
[patent_no_of_claims] => 56
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/471/05471633.pdf
[firstpage_image] =>[orig_patent_app_number] => 205842
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/205842 | Idiom recognizer within a register alias table | Feb 28, 1994 | Issued |
Array
(
[id] => 3082814
[patent_doc_number] => 05361376
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-11-01
[patent_title] => 'Keyboard and controller with a three wire half duplex asynchronous and bidirectional communications architecture'
[patent_app_type] => 1
[patent_app_number] => 8/203831
[patent_app_country] => US
[patent_app_date] => 1994-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 14
[patent_no_of_words] => 6681
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/361/05361376.pdf
[firstpage_image] =>[orig_patent_app_number] => 203831
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/203831 | Keyboard and controller with a three wire half duplex asynchronous and bidirectional communications architecture | Feb 27, 1994 | Issued |
| 08/201566 | REGISTER ALIAS TABLE UPDATE TO INDICATE ARCHITECTURALLY VISIBLE STATE | Feb 24, 1994 | Abandoned |
Array
(
[id] => 3439155
[patent_doc_number] => 05404565
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-04-04
[patent_title] => 'Message tracking in a parallel network employing a status word at each node which reflects a message\'s progress'
[patent_app_type] => 1
[patent_app_number] => 8/197004
[patent_app_country] => US
[patent_app_date] => 1994-02-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/05/404/05404565.pdf
[firstpage_image] =>[orig_patent_app_number] => 197004
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/197004 | Message tracking in a parallel network employing a status word at each node which reflects a message's progress | Feb 14, 1994 | Issued |
Array
(
[id] => 3544049
[patent_doc_number] => 05583993
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-10
[patent_title] => 'Method and apparatus for synchronously sharing data among computer'
[patent_app_type] => 1
[patent_app_number] => 8/189104
[patent_app_country] => US
[patent_app_date] => 1994-01-31
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/583/05583993.pdf
[firstpage_image] =>[orig_patent_app_number] => 189104
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/189104 | Method and apparatus for synchronously sharing data among computer | Jan 30, 1994 | Issued |
Array
(
[id] => 3605553
[patent_doc_number] => 05522042
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-28
[patent_title] => 'Distributed chassis agent for distributed network management'
[patent_app_type] => 1
[patent_app_number] => 8/187856
[patent_app_country] => US
[patent_app_date] => 1994-01-28
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[pdf_file] => patents/05/522/05522042.pdf
[firstpage_image] =>[orig_patent_app_number] => 187856
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/187856 | Distributed chassis agent for distributed network management | Jan 27, 1994 | Issued |
