Search

Gerald G. Leffers Jr.

Examiner (ID: 894)

Most Active Art Unit
1636
Art Unit(s)
1636
Total Applications
331
Issued Applications
154
Pending Applications
90
Abandoned Applications
87

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3082794 [patent_doc_number] => 05361375 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-01 [patent_title] => 'Virtual computer system having input/output interrupt control of virtual machines' [patent_app_type] => 1 [patent_app_number] => 8/065685 [patent_app_country] => US [patent_app_date] => 1993-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4580 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 447 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/361/05361375.pdf [firstpage_image] =>[orig_patent_app_number] => 065685 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/065685
Virtual computer system having input/output interrupt control of virtual machines May 23, 1993 Issued
Array ( [id] => 3016221 [patent_doc_number] => 05371896 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-06 [patent_title] => 'Multi-processor having control over synchronization of processors in mind mode and method of operation' [patent_app_type] => 1 [patent_app_number] => 8/062867 [patent_app_country] => US [patent_app_date] => 1993-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 64 [patent_no_of_words] => 37525 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/371/05371896.pdf [firstpage_image] =>[orig_patent_app_number] => 062867 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/062867
Multi-processor having control over synchronization of processors in mind mode and method of operation May 16, 1993 Issued
Array ( [id] => 3589399 [patent_doc_number] => 05524256 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-04 [patent_title] => 'Method and system for reordering bytes in a data stream' [patent_app_type] => 1 [patent_app_number] => 8/058429 [patent_app_country] => US [patent_app_date] => 1993-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 5308 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 344 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/524/05524256.pdf [firstpage_image] =>[orig_patent_app_number] => 058429 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/058429
Method and system for reordering bytes in a data stream May 6, 1993 Issued
Array ( [id] => 3676981 [patent_doc_number] => 05598568 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-28 [patent_title] => 'Multicomputer memory access architecture' [patent_app_type] => 1 [patent_app_number] => 8/058485 [patent_app_country] => US [patent_app_date] => 1993-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 15507 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 474 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/598/05598568.pdf [firstpage_image] =>[orig_patent_app_number] => 058485 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/058485
Multicomputer memory access architecture May 5, 1993 Issued
08/040675 METHOD AND APPARATUS FOR DYNAMICALLY EXPANDING THE PIPELINE OF A MICROPROCESSOR Mar 30, 1993 Pending
Array ( [id] => 3532998 [patent_doc_number] => 05530882 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-25 [patent_title] => 'Multi-purpose information processing system' [patent_app_type] => 1 [patent_app_number] => 8/038215 [patent_app_country] => US [patent_app_date] => 1993-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2634 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/530/05530882.pdf [firstpage_image] =>[orig_patent_app_number] => 038215 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/038215
Multi-purpose information processing system Mar 28, 1993 Issued
Array ( [id] => 3063011 [patent_doc_number] => 05283889 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-01 [patent_title] => 'Hardware based interface for mode switching to access memory above one megabyte' [patent_app_type] => 1 [patent_app_number] => 8/031029 [patent_app_country] => US [patent_app_date] => 1993-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 21887 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/283/05283889.pdf [firstpage_image] =>[orig_patent_app_number] => 031029 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/031029
Hardware based interface for mode switching to access memory above one megabyte Mar 10, 1993 Issued
Array ( [id] => 3506505 [patent_doc_number] => 05537623 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-16 [patent_title] => 'Multiple group address recognition' [patent_app_type] => 1 [patent_app_number] => 8/024593 [patent_app_country] => US [patent_app_date] => 1993-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 5974 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/537/05537623.pdf [firstpage_image] =>[orig_patent_app_number] => 024593 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/024593
Multiple group address recognition Feb 28, 1993 Issued
Array ( [id] => 3576877 [patent_doc_number] => 05483657 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-09 [patent_title] => 'Method of controlling execution of a data flow program and apparatus therefor' [patent_app_type] => 1 [patent_app_number] => 8/022265 [patent_app_country] => US [patent_app_date] => 1993-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 8969 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 481 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/483/05483657.pdf [firstpage_image] =>[orig_patent_app_number] => 022265 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/022265
Method of controlling execution of a data flow program and apparatus therefor Feb 24, 1993 Issued
Array ( [id] => 3095413 [patent_doc_number] => 05280621 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-18 [patent_title] => 'Personal computer having dedicated processors for peripheral devices interconnected to the CPU by way of a system control processor' [patent_app_type] => 1 [patent_app_number] => 8/019997 [patent_app_country] => US [patent_app_date] => 1993-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4774 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/280/05280621.pdf [firstpage_image] =>[orig_patent_app_number] => 019997 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/019997
Personal computer having dedicated processors for peripheral devices interconnected to the CPU by way of a system control processor Feb 16, 1993 Issued
08/027234 DATA PROCESSING APPARATUS FOR EXECUTING A VECTOR OPERATION UNDER CONTROL OF A MASTER PROCESSOR Jan 27, 1993 Abandoned
Array ( [id] => 3025420 [patent_doc_number] => 05276903 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-04 [patent_title] => 'Method for rewriting partial program data in an IC card and apparatus therefor' [patent_app_type] => 1 [patent_app_number] => 8/003945 [patent_app_country] => US [patent_app_date] => 1993-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 3851 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 392 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/276/05276903.pdf [firstpage_image] =>[orig_patent_app_number] => 003945 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/003945
Method for rewriting partial program data in an IC card and apparatus therefor Jan 18, 1993 Issued
Array ( [id] => 3454851 [patent_doc_number] => 05467473 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-14 [patent_title] => 'Out of order instruction load and store comparison' [patent_app_type] => 1 [patent_app_number] => 8/001976 [patent_app_country] => US [patent_app_date] => 1993-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5399 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/467/05467473.pdf [firstpage_image] =>[orig_patent_app_number] => 001976 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/001976
Out of order instruction load and store comparison Jan 7, 1993 Issued
Array ( [id] => 4040386 [patent_doc_number] => 05884054 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'Multiprocessor system including interprocessor encoding and decoding logic for communication between two cards through reduced addressing lines' [patent_app_type] => 1 [patent_app_number] => 8/001091 [patent_app_country] => US [patent_app_date] => 1993-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5785 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/884/05884054.pdf [firstpage_image] =>[orig_patent_app_number] => 001091 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/001091
Multiprocessor system including interprocessor encoding and decoding logic for communication between two cards through reduced addressing lines Jan 5, 1993 Issued
Array ( [id] => 3129822 [patent_doc_number] => 05410721 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-25 [patent_title] => 'System and method for incrementing a program counter' [patent_app_type] => 1 [patent_app_number] => 7/996749 [patent_app_country] => US [patent_app_date] => 1992-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6636 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/410/05410721.pdf [firstpage_image] =>[orig_patent_app_number] => 996749 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/996749
System and method for incrementing a program counter Dec 23, 1992 Issued
Array ( [id] => 2964000 [patent_doc_number] => 05263174 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-16 [patent_title] => 'Methods for quick selection of desired items from hierarchical computer menus' [patent_app_type] => 1 [patent_app_number] => 7/993900 [patent_app_country] => US [patent_app_date] => 1992-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 1783 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/263/05263174.pdf [firstpage_image] =>[orig_patent_app_number] => 993900 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/993900
Methods for quick selection of desired items from hierarchical computer menus Dec 17, 1992 Issued
Array ( [id] => 3041995 [patent_doc_number] => 05349688 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-20 [patent_title] => 'Method for reducing power consumption includes comparing variance in number of times microprocessor tried to read input in predefined period to predefined variance' [patent_app_type] => 1 [patent_app_number] => 7/989249 [patent_app_country] => US [patent_app_date] => 1992-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2911 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/349/05349688.pdf [firstpage_image] =>[orig_patent_app_number] => 989249 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/989249
Method for reducing power consumption includes comparing variance in number of times microprocessor tried to read input in predefined period to predefined variance Dec 10, 1992 Issued
Array ( [id] => 2915980 [patent_doc_number] => 05249300 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-28 [patent_title] => 'System and method of constructing models of complex business transactions using entity-set variables for ordered sets of references to user data' [patent_app_type] => 1 [patent_app_number] => 7/982153 [patent_app_country] => US [patent_app_date] => 1992-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 38 [patent_no_of_words] => 12375 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/249/05249300.pdf [firstpage_image] =>[orig_patent_app_number] => 982153 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/982153
System and method of constructing models of complex business transactions using entity-set variables for ordered sets of references to user data Nov 24, 1992 Issued
Array ( [id] => 4381524 [patent_doc_number] => 06256726 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Data processor for the parallel processing of a plurality of instructions' [patent_app_type] => 1 [patent_app_number] => 7/979772 [patent_app_country] => US [patent_app_date] => 1992-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 39 [patent_no_of_words] => 7532 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256726.pdf [firstpage_image] =>[orig_patent_app_number] => 979772 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/979772
Data processor for the parallel processing of a plurality of instructions Nov 19, 1992 Issued
Array ( [id] => 3107957 [patent_doc_number] => 05291587 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-01 [patent_title] => 'Graphical system for executing a process and for programming a computer to execute a process, including graphical variable inputs and variable outputs' [patent_app_type] => 1 [patent_app_number] => 7/979416 [patent_app_country] => US [patent_app_date] => 1992-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 90 [patent_no_of_words] => 18211 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/291/05291587.pdf [firstpage_image] =>[orig_patent_app_number] => 979416 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/979416
Graphical system for executing a process and for programming a computer to execute a process, including graphical variable inputs and variable outputs Nov 18, 1992 Issued
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