Gerald G. Leffers Jr.

Array ( [id] => 2947088 [patent_doc_number] => 05220675 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-15 [patent_title] => 'Method and system for customizing a user interface in an integrated environment' [patent_app_type] => 1 [patent_app_number] => 7/840656 [patent_app_country] => US [patent_app_date] => 1992-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 3 [patent_no_of_words] => 4947 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/220/05220675.pdf [firstpage_image] =>[orig_patent_app_number] => 840656 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3460962 [patent_doc_number] => 05386580 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-31 [patent_title] => 'Data processor' [patent_app_type] => 1 [patent_app_number] => 7/819545 [patent_app_country] => US [patent_app_date] => 1992-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 44 [patent_no_of_words] => 17603 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 340 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/386/05386580.pdf [firstpage_image] =>[orig_patent_app_number] => 819545 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3122407 [patent_doc_number] => 05408637 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-18 [patent_title] => 'Emulation techniques giving necessary information to a microcomputer to perform software debug and system debug even for incomplete target system' [patent_app_type] => 1 [patent_app_number] => 7/806643 [patent_app_country] => US [patent_app_date] => 1991-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 8316 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/408/05408637.pdf [firstpage_image] =>[orig_patent_app_number] => 806643 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3008294 [patent_doc_number] => 05367699 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-22 [patent_title] => 'Central processing unit incorporation selectable, precisa ratio, speed of execution derating' [patent_app_type] => 1 [patent_app_number] => 7/800343 [patent_app_country] => US [patent_app_date] => 1991-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3211 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 467 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/367/05367699.pdf [firstpage_image] =>[orig_patent_app_number] => 800343 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3424365 [patent_doc_number] => 05412794 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-02 [patent_title] => 'Microprocessor based systems providing simulated low voltage conditions for testing reset circuits' [patent_app_type] => 1 [patent_app_number] => 7/789839 [patent_app_country] => US [patent_app_date] => 1991-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3650 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/412/05412794.pdf [firstpage_image] =>[orig_patent_app_number] => 789839 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2843193 [patent_doc_number] => 05175845 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-29 [patent_title] => 'Integrated circuit with watchdog timer and sleep control logic which places IC and watchdog timer into sleep mode' [patent_app_type] => 1 [patent_app_number] => 7/785892 [patent_app_country] => US [patent_app_date] => 1991-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 6769 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/175/05175845.pdf [firstpage_image] =>[orig_patent_app_number] => 785892 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3434026 [patent_doc_number] => 05390352 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-14 [patent_title] => 'Vector processing device comprising a single supplying circuit for use in both stride and indirect vector processing modes' [patent_app_type] => 1 [patent_app_number] => 7/768040 [patent_app_country] => US [patent_app_date] => 1991-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5590 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 357 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/390/05390352.pdf [firstpage_image] =>[orig_patent_app_number] => 768040 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3016203 [patent_doc_number] => 05371895 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-06 [patent_title] => 'Local equipment controller for computerized process control applications utilizing language structure templates in a hierarchical organization and method of operating the same' [patent_app_type] => 1 [patent_app_number] => 7/769116 [patent_app_country] => US [patent_app_date] => 1991-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 35 [patent_no_of_words] => 13521 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/371/05371895.pdf [firstpage_image] =>[orig_patent_app_number] => 769116 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2929773 [patent_doc_number] => 05193157 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-09 [patent_title] => 'Piplined system includes a selector for loading condition code either from first or second condition code registers to program counter' [patent_app_type] => 1 [patent_app_number] => 7/769165 [patent_app_country] => US [patent_app_date] => 1991-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3378 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/193/05193157.pdf [firstpage_image] =>[orig_patent_app_number] => 769165 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3008202 [patent_doc_number] => 05367694 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-22 [patent_title] => 'RISC processor having a cross-bar switch' [patent_app_type] => 1 [patent_app_number] => 7/750940 [patent_app_country] => US [patent_app_date] => 1991-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1665 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/367/05367694.pdf [firstpage_image] =>[orig_patent_app_number] => 750940 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3003627 [patent_doc_number] => 05347613 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-13 [patent_title] => 'MOS multi-layer neural network including a plurality of hidden layers interposed between synapse groups for performing pattern recognition' [patent_app_type] => 1 [patent_app_number] => 7/745346 [patent_app_country] => US [patent_app_date] => 1991-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3691 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 764 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/347/05347613.pdf [firstpage_image] =>[orig_patent_app_number] => 745346 [rel_patent_id] =>[rel_patent_doc_number] =>)