Search

Gerald G. Leffers Jr.

Examiner (ID: 894)

Most Active Art Unit
1636
Art Unit(s)
1636
Total Applications
331
Issued Applications
154
Pending Applications
90
Abandoned Applications
87

Applications

Application numberTitle of the applicationFiling DateStatus
07/486521 CENTRALIZED DATA COMMUNICATION SYSTEM INCLUDING INTERFACE UNITS ARRANGED FOR CUSTOM OPERATION Feb 27, 1990 Abandoned
Array ( [id] => 3032986 [patent_doc_number] => 05303376 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-12 [patent_title] => 'Program partial linking system for linking a specific program prepared in advance when an assigned program is not in a program library' [patent_app_type] => 1 [patent_app_number] => 7/484486 [patent_app_country] => US [patent_app_date] => 1990-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1877 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/303/05303376.pdf [firstpage_image] =>[orig_patent_app_number] => 484486 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/484486
Program partial linking system for linking a specific program prepared in advance when an assigned program is not in a program library Feb 25, 1990 Issued
07/477547 VIRTUAL COMPUTER SYSTEM HAVING INPUT/OUTPUT INTERRUPT CONTROL OF VIRTUAL MACHINES Feb 8, 1990 Abandoned
07/477549 MICROPROCESSOR HAVING STORE BUFFER TO ACCESS EXTERNAL MEMORY Feb 8, 1990 Abandoned
Array ( [id] => 2946923 [patent_doc_number] => 05197147 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-23 [patent_title] => 'Keycode translation system for producing translated keycode signals responsive to keyboard signals which act as a pointer to keycode translation table' [patent_app_type] => 1 [patent_app_number] => 7/474917 [patent_app_country] => US [patent_app_date] => 1990-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2531 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/197/05197147.pdf [firstpage_image] =>[orig_patent_app_number] => 474917 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/474917
Keycode translation system for producing translated keycode signals responsive to keyboard signals which act as a pointer to keycode translation table Feb 4, 1990 Issued
Array ( [id] => 2849708 [patent_doc_number] => 05121473 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-09 [patent_title] => 'Pipelined system includes correction mechanism operated on history information identifying conditional jump instructions for which the jump prediction was incorrect on previous instances of execution of those instructions' [patent_app_type] => 1 [patent_app_number] => 7/474297 [patent_app_country] => US [patent_app_date] => 1990-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3314 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/121/05121473.pdf [firstpage_image] =>[orig_patent_app_number] => 474297 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/474297
Pipelined system includes correction mechanism operated on history information identifying conditional jump instructions for which the jump prediction was incorrect on previous instances of execution of those instructions Feb 1, 1990 Issued
Array ( [id] => 2795606 [patent_doc_number] => 05165036 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-17 [patent_title] => 'Parallel processing development system with debugging device includes facilities for schematically displaying execution state of data driven type processor' [patent_app_type] => 1 [patent_app_number] => 7/471204 [patent_app_country] => US [patent_app_date] => 1990-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 7179 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/165/05165036.pdf [firstpage_image] =>[orig_patent_app_number] => 471204 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/471204
Parallel processing development system with debugging device includes facilities for schematically displaying execution state of data driven type processor Jan 28, 1990 Issued
Array ( [id] => 2826290 [patent_doc_number] => 05123094 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-16 [patent_title] => 'Interprocessor communications includes second CPU designating memory locations assigned to first CPU and writing their addresses into registers' [patent_app_type] => 1 [patent_app_number] => 7/471093 [patent_app_country] => US [patent_app_date] => 1990-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 5067 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/123/05123094.pdf [firstpage_image] =>[orig_patent_app_number] => 471093 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/471093
Interprocessor communications includes second CPU designating memory locations assigned to first CPU and writing their addresses into registers Jan 25, 1990 Issued
07/462501 METHOD AND SYSTEM FOR USER CUSTOMIZING OF MENUS IN A COMPUTER SYSTEM Jan 7, 1990 Abandoned
07/459055 PAST SWITCHING MEMORY MODE SYSTEM Dec 28, 1989 Abandoned
07/459042 PERIPHERAL CONTROLLER NETWORK FOR PERSONAL COMPUTERS Dec 28, 1989 Abandoned
Array ( [id] => 2843444 [patent_doc_number] => 05175857 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-29 [patent_title] => 'System for sorting records having sorted strings each having a plurality of linked elements each element storing next record address' [patent_app_type] => 1 [patent_app_number] => 7/458361 [patent_app_country] => US [patent_app_date] => 1989-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 4229 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/175/05175857.pdf [firstpage_image] =>[orig_patent_app_number] => 458361 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/458361
System for sorting records having sorted strings each having a plurality of linked elements each element storing next record address Dec 27, 1989 Issued
Array ( [id] => 2850224 [patent_doc_number] => 05121501 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-09 [patent_title] => 'First processor inserting hooks into software and sending unique identifications to output bus and second processor associating data frames and time with these unique identifications' [patent_app_type] => 1 [patent_app_number] => 7/458045 [patent_app_country] => US [patent_app_date] => 1989-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3771 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/121/05121501.pdf [firstpage_image] =>[orig_patent_app_number] => 458045 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/458045
First processor inserting hooks into software and sending unique identifications to output bus and second processor associating data frames and time with these unique identifications Dec 26, 1989 Issued
Array ( [id] => 2861381 [patent_doc_number] => 05134562 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-28 [patent_title] => 'Fifo register device adaptively changing a stage number in dependency on a bus cycle' [patent_app_type] => 1 [patent_app_number] => 7/448083 [patent_app_country] => US [patent_app_date] => 1989-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4985 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 394 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/134/05134562.pdf [firstpage_image] =>[orig_patent_app_number] => 448083 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/448083
Fifo register device adaptively changing a stage number in dependency on a bus cycle Dec 11, 1989 Issued
Array ( [id] => 2998551 [patent_doc_number] => 05212777 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-05-18 [patent_title] => 'Multi-processor reconfigurable in single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD) modes and method of operation' [patent_app_type] => 1 [patent_app_number] => 7/437858 [patent_app_country] => US [patent_app_date] => 1989-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 64 [patent_no_of_words] => 37114 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 541 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/212/05212777.pdf [firstpage_image] =>[orig_patent_app_number] => 437858 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/437858
Multi-processor reconfigurable in single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD) modes and method of operation Nov 16, 1989 Issued
Array ( [id] => 2703845 [patent_doc_number] => 05065359 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-11-12 [patent_title] => 'Desk top calculator with access sequence control system for various constants' [patent_app_type] => 1 [patent_app_number] => 7/436905 [patent_app_country] => US [patent_app_date] => 1989-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2435 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/065/05065359.pdf [firstpage_image] =>[orig_patent_app_number] => 436905 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/436905
Desk top calculator with access sequence control system for various constants Nov 14, 1989 Issued
Array ( [id] => 2934387 [patent_doc_number] => 05201059 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-06 [patent_title] => 'Method for reducing power consumption includes comparing variance in number of time microprocessor tried to react input in predefined period to predefined variance' [patent_app_type] => 1 [patent_app_number] => 7/434200 [patent_app_country] => US [patent_app_date] => 1989-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2919 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/201/05201059.pdf [firstpage_image] =>[orig_patent_app_number] => 434200 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/434200
Method for reducing power consumption includes comparing variance in number of time microprocessor tried to react input in predefined period to predefined variance Nov 12, 1989 Issued
Array ( [id] => 2945222 [patent_doc_number] => 05233694 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-03 [patent_title] => 'Pipelined data processor capable of performing instruction fetch stages of a plurality of instructions simultaneously' [patent_app_type] => 1 [patent_app_number] => 7/433368 [patent_app_country] => US [patent_app_date] => 1989-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 39 [patent_no_of_words] => 7536 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 331 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/233/05233694.pdf [firstpage_image] =>[orig_patent_app_number] => 433368 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/433368
Pipelined data processor capable of performing instruction fetch stages of a plurality of instructions simultaneously Nov 7, 1989 Issued
Array ( [id] => 2934275 [patent_doc_number] => 05201055 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-06 [patent_title] => 'Multiprocessing system includes interprocessor encoding and decoding logic used for communication between two cards through reduced addressing lines' [patent_app_type] => 1 [patent_app_number] => 7/431659 [patent_app_country] => US [patent_app_date] => 1989-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5833 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/201/05201055.pdf [firstpage_image] =>[orig_patent_app_number] => 431659 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/431659
Multiprocessing system includes interprocessor encoding and decoding logic used for communication between two cards through reduced addressing lines Nov 2, 1989 Issued
Array ( [id] => 2843156 [patent_doc_number] => 05175843 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-29 [patent_title] => 'Computer-aided design method for restructuring computational networks to minimize shimming delays' [patent_app_type] => 1 [patent_app_number] => 7/428808 [patent_app_country] => US [patent_app_date] => 1989-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 40 [patent_no_of_words] => 12696 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/175/05175843.pdf [firstpage_image] =>[orig_patent_app_number] => 428808 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/428808
Computer-aided design method for restructuring computational networks to minimize shimming delays Oct 29, 1989 Issued
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