Search

Gerald G. Leffers Jr.

Examiner (ID: 894)

Most Active Art Unit
1636
Art Unit(s)
1636
Total Applications
331
Issued Applications
154
Pending Applications
90
Abandoned Applications
87

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2843717 [patent_doc_number] => 05129065 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-07 [patent_title] => 'Apparatus and methods for interface register handshake for controlling devices' [patent_app_type] => 1 [patent_app_number] => 7/428236 [patent_app_country] => US [patent_app_date] => 1989-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3642 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/129/05129065.pdf [firstpage_image] =>[orig_patent_app_number] => 428236 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/428236
Apparatus and methods for interface register handshake for controlling devices Oct 26, 1989 Issued
Array ( [id] => 2798943 [patent_doc_number] => 05142686 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-25 [patent_title] => 'Multiprocessor system having processors and switches with each pair of processors connected through a single switch using Latin square matrix' [patent_app_type] => 1 [patent_app_number] => 7/424776 [patent_app_country] => US [patent_app_date] => 1989-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4892 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/142/05142686.pdf [firstpage_image] =>[orig_patent_app_number] => 424776 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/424776
Multiprocessor system having processors and switches with each pair of processors connected through a single switch using Latin square matrix Oct 19, 1989 Issued
07/420678 APPARATUS AND METHOD FOR CONTROLLING THE TRANSFER OF DIGITAL INFORMA- TION BETWEEN SERVICE PROCESSORS OF A COMPUTER Oct 9, 1989 Abandoned
Array ( [id] => 2849557 [patent_doc_number] => 05161217 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-03 [patent_title] => 'Buffered address stack register with parallel input registers and overflow protection' [patent_app_type] => 1 [patent_app_number] => 7/418084 [patent_app_country] => US [patent_app_date] => 1989-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6076 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/161/05161217.pdf [firstpage_image] =>[orig_patent_app_number] => 418084 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/418084
Buffered address stack register with parallel input registers and overflow protection Oct 5, 1989 Issued
Array ( [id] => 2795432 [patent_doc_number] => 05165026 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-17 [patent_title] => 'Programmable controller in which fetching of operand data and fetching of operand addresses are simultaneously performed' [patent_app_type] => 1 [patent_app_number] => 7/417039 [patent_app_country] => US [patent_app_date] => 1989-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 26 [patent_no_of_words] => 4233 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 432 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/165/05165026.pdf [firstpage_image] =>[orig_patent_app_number] => 417039 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/417039
Programmable controller in which fetching of operand data and fetching of operand addresses are simultaneously performed Oct 3, 1989 Issued
Array ( [id] => 2799842 [patent_doc_number] => 05155856 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-13 [patent_title] => 'Arrangement in a self-guarding data processing system for system initialization and reset' [patent_app_type] => 1 [patent_app_number] => 7/401332 [patent_app_country] => US [patent_app_date] => 1989-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3039 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/155/05155856.pdf [firstpage_image] =>[orig_patent_app_number] => 401332 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/401332
Arrangement in a self-guarding data processing system for system initialization and reset Aug 30, 1989 Issued
Array ( [id] => 2813597 [patent_doc_number] => 05115393 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-19 [patent_title] => 'Vector processor performing data operations in one half of a total time period of write operation and the read operation' [patent_app_type] => 1 [patent_app_number] => 7/399917 [patent_app_country] => US [patent_app_date] => 1989-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6018 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/115/05115393.pdf [firstpage_image] =>[orig_patent_app_number] => 399917 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/399917
Vector processor performing data operations in one half of a total time period of write operation and the read operation Aug 28, 1989 Issued
Array ( [id] => 2822679 [patent_doc_number] => 05079692 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-01-07 [patent_title] => 'Controller which allows direct access by processor to peripheral units' [patent_app_type] => 1 [patent_app_number] => 7/399413 [patent_app_country] => US [patent_app_date] => 1989-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3922 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/079/05079692.pdf [firstpage_image] =>[orig_patent_app_number] => 399413 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/399413
Controller which allows direct access by processor to peripheral units Aug 24, 1989 Issued
Array ( [id] => 2889667 [patent_doc_number] => 05159675 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-27 [patent_title] => 'Performance control mechanism for alternately allowing instructions to be initiated for R clock beats and preventing initiating thereof for W clock beats' [patent_app_type] => 1 [patent_app_number] => 7/393418 [patent_app_country] => US [patent_app_date] => 1989-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1090 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/159/05159675.pdf [firstpage_image] =>[orig_patent_app_number] => 393418 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/393418
Performance control mechanism for alternately allowing instructions to be initiated for R clock beats and preventing initiating thereof for W clock beats Aug 13, 1989 Issued
07/391983 IC CARD AND METHOD FOR REWRITING ITS PROGRAM Aug 9, 1989 Abandoned
Array ( [id] => 2790026 [patent_doc_number] => 05088030 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-02-11 [patent_title] => 'Branch address calculating system for branch instructions' [patent_app_type] => 1 [patent_app_number] => 7/391665 [patent_app_country] => US [patent_app_date] => 1989-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2118 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/088/05088030.pdf [firstpage_image] =>[orig_patent_app_number] => 391665 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/391665
Branch address calculating system for branch instructions Aug 7, 1989 Issued
Array ( [id] => 2878510 [patent_doc_number] => 05097483 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-17 [patent_title] => 'Tri-statable bus with apparatus to drive bus line to first level and then second level for predetermined time before turning off' [patent_app_type] => 1 [patent_app_number] => 7/387227 [patent_app_country] => US [patent_app_date] => 1989-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 5676 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/097/05097483.pdf [firstpage_image] =>[orig_patent_app_number] => 387227 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/387227
Tri-statable bus with apparatus to drive bus line to first level and then second level for predetermined time before turning off Jul 27, 1989 Issued
07/376257 GRAPHICAL SYSTEM FOR EXECUTING A PROCESS AND FOR PROGRAMMING A COMPUTER TO EXECUTE A POCESS Jul 5, 1989 Abandoned
Array ( [id] => 2816975 [patent_doc_number] => 05146574 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-08 [patent_title] => 'Method and circuit for programmable selecting a variable sequence of element using write-back' [patent_app_type] => 1 [patent_app_number] => 7/372278 [patent_app_country] => US [patent_app_date] => 1989-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 4863 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 343 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/146/05146574.pdf [firstpage_image] =>[orig_patent_app_number] => 372278 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/372278
Method and circuit for programmable selecting a variable sequence of element using write-back Jun 26, 1989 Issued
Array ( [id] => 2885378 [patent_doc_number] => 05185694 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-09 [patent_title] => 'Data processing system utilizes block move instruction for burst transferring blocks of data entries where width of data blocks varies' [patent_app_type] => 1 [patent_app_number] => 7/371343 [patent_app_country] => US [patent_app_date] => 1989-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2587 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/185/05185694.pdf [firstpage_image] =>[orig_patent_app_number] => 371343 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/371343
Data processing system utilizes block move instruction for burst transferring blocks of data entries where width of data blocks varies Jun 25, 1989 Issued
Array ( [id] => 2905191 [patent_doc_number] => 05210854 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-05-11 [patent_title] => 'System for updating program stored in EEPROM by storing new version into new location and updating second transfer vector to contain starting address of new version' [patent_app_type] => 1 [patent_app_number] => 7/366168 [patent_app_country] => US [patent_app_date] => 1989-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4468 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/210/05210854.pdf [firstpage_image] =>[orig_patent_app_number] => 366168 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/366168
System for updating program stored in EEPROM by storing new version into new location and updating second transfer vector to contain starting address of new version Jun 13, 1989 Issued
Array ( [id] => 2793983 [patent_doc_number] => 05093777 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-03 [patent_title] => 'Method and apparatus for predicting address of a subsequent cache request upon analyzing address patterns stored in separate miss stack' [patent_app_type] => 1 [patent_app_number] => 7/364943 [patent_app_country] => US [patent_app_date] => 1989-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2918 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/093/05093777.pdf [firstpage_image] =>[orig_patent_app_number] => 364943 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/364943
Method and apparatus for predicting address of a subsequent cache request upon analyzing address patterns stored in separate miss stack Jun 11, 1989 Issued
Array ( [id] => 2788190 [patent_doc_number] => 05133060 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-21 [patent_title] => 'Disk controller includes cache memory and a local processor which limits data transfers from memory to cache in accordance with a maximum look ahead parameter' [patent_app_type] => 1 [patent_app_number] => 7/361227 [patent_app_country] => US [patent_app_date] => 1989-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4160 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/133/05133060.pdf [firstpage_image] =>[orig_patent_app_number] => 361227 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/361227
Disk controller includes cache memory and a local processor which limits data transfers from memory to cache in accordance with a maximum look ahead parameter Jun 4, 1989 Issued
Array ( [id] => 2820074 [patent_doc_number] => 05086407 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-02-04 [patent_title] => 'Data processor integrated circuit with selectable multiplexed/non-multiplexed address and data modes of operation' [patent_app_type] => 1 [patent_app_number] => 7/361539 [patent_app_country] => US [patent_app_date] => 1989-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3799 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/086/05086407.pdf [firstpage_image] =>[orig_patent_app_number] => 361539 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/361539
Data processor integrated circuit with selectable multiplexed/non-multiplexed address and data modes of operation Jun 4, 1989 Issued
07/356170 MULTIPLE INSTRUCTION ISSUE AND EXECUTION COMPUTER ARCHITECTURE May 23, 1989 Abandoned
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