Search

Gerald G. Leffers Jr.

Examiner (ID: 894)

Most Active Art Unit
1636
Art Unit(s)
1636
Total Applications
331
Issued Applications
154
Pending Applications
90
Abandoned Applications
87

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2892707 [patent_doc_number] => 05109503 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-28 [patent_title] => 'Apparatus with reconfigurable counter includes memory for storing plurality of counter configuration files which respectively define plurality of predetermined counters' [patent_app_type] => 1 [patent_app_number] => 7/355266 [patent_app_country] => US [patent_app_date] => 1989-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 9694 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/109/05109503.pdf [firstpage_image] =>[orig_patent_app_number] => 355266 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/355266
Apparatus with reconfigurable counter includes memory for storing plurality of counter configuration files which respectively define plurality of predetermined counters May 21, 1989 Issued
Array ( [id] => 2861634 [patent_doc_number] => 05089984 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-02-18 [patent_title] => 'Adaptive alarm controller changes multiple inputs to industrial controller in order for state word to conform with stored state word' [patent_app_type] => 1 [patent_app_number] => 7/352189 [patent_app_country] => US [patent_app_date] => 1989-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 6457 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/089/05089984.pdf [firstpage_image] =>[orig_patent_app_number] => 352189 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/352189
Adaptive alarm controller changes multiple inputs to industrial controller in order for state word to conform with stored state word May 14, 1989 Issued
Array ( [id] => 2798925 [patent_doc_number] => 05142685 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-25 [patent_title] => 'Pipeline circuit for timing adjustment of irregular valid and invalid data' [patent_app_type] => 1 [patent_app_number] => 7/351084 [patent_app_country] => US [patent_app_date] => 1989-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 17655 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/142/05142685.pdf [firstpage_image] =>[orig_patent_app_number] => 351084 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/351084
Pipeline circuit for timing adjustment of irregular valid and invalid data May 11, 1989 Issued
Array ( [id] => 2817490 [patent_doc_number] => 05146600 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-08 [patent_title] => 'Document image filing system for furnishing additional managerial information for management of documents filed in the system' [patent_app_type] => 1 [patent_app_number] => 7/345794 [patent_app_country] => US [patent_app_date] => 1989-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 28 [patent_no_of_words] => 11682 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/146/05146600.pdf [firstpage_image] =>[orig_patent_app_number] => 345794 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/345794
Document image filing system for furnishing additional managerial information for management of documents filed in the system Apr 30, 1989 Issued
07/344492 COMPUTER LANGUAGE STRUCTURE FOR PROCESS CONTROL APPLICATIONS, AND METHOD OF TRANSLATING SAME INTO PROGRAM CODE TO OPERATE THE COMPUTER Apr 25, 1989 Abandoned
Array ( [id] => 2797701 [patent_doc_number] => 05142630 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-25 [patent_title] => 'System for calculating branch destination address based upon address mode bit in operand before executing an instruction which changes the address mode and branching' [patent_app_type] => 1 [patent_app_number] => 7/340084 [patent_app_country] => US [patent_app_date] => 1989-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2291 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/142/05142630.pdf [firstpage_image] =>[orig_patent_app_number] => 340084 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/340084
System for calculating branch destination address based upon address mode bit in operand before executing an instruction which changes the address mode and branching Apr 17, 1989 Issued
07/333974 CONTROLLER FOR A STORAGE DEVICE Apr 5, 1989 Abandoned
Array ( [id] => 2927549 [patent_doc_number] => 05179671 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-01-12 [patent_title] => 'Apparatus for generating first and second selection signals for aligning words of an operand and bytes within these words respectively' [patent_app_type] => 1 [patent_app_number] => 7/331991 [patent_app_country] => US [patent_app_date] => 1989-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5686 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/179/05179671.pdf [firstpage_image] =>[orig_patent_app_number] => 331991 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/331991
Apparatus for generating first and second selection signals for aligning words of an operand and bytes within these words respectively Mar 30, 1989 Issued
Array ( [id] => 2892994 [patent_doc_number] => 05109519 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-28 [patent_title] => 'Local computer participating in mail delivery system abstracts from directory of all eligible mail recipients only served by local computer' [patent_app_type] => 1 [patent_app_number] => 7/329744 [patent_app_country] => US [patent_app_date] => 1989-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2478 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/109/05109519.pdf [firstpage_image] =>[orig_patent_app_number] => 329744 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/329744
Local computer participating in mail delivery system abstracts from directory of all eligible mail recipients only served by local computer Mar 27, 1989 Issued
Array ( [id] => 2715659 [patent_doc_number] => 05068821 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-11-26 [patent_title] => 'Bit processor with powers flow register switches control a function block processor for execution of the current command' [patent_app_type] => 1 [patent_app_number] => 7/329151 [patent_app_country] => US [patent_app_date] => 1989-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4308 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/068/05068821.pdf [firstpage_image] =>[orig_patent_app_number] => 329151 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/329151
Bit processor with powers flow register switches control a function block processor for execution of the current command Mar 26, 1989 Issued
Array ( [id] => 2939853 [patent_doc_number] => 05187794 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-16 [patent_title] => 'System for simultaneously loading program to master computer memory devices and corresponding slave computer memory devices' [patent_app_type] => 1 [patent_app_number] => 7/323748 [patent_app_country] => US [patent_app_date] => 1989-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4228 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/187/05187794.pdf [firstpage_image] =>[orig_patent_app_number] => 323748 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/323748
System for simultaneously loading program to master computer memory devices and corresponding slave computer memory devices Mar 14, 1989 Issued
Array ( [id] => 2847351 [patent_doc_number] => 05161102 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-03 [patent_title] => 'Computer interface for the configuration of computer system and circuit boards' [patent_app_type] => 1 [patent_app_number] => 7/311021 [patent_app_country] => US [patent_app_date] => 1989-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 24 [patent_no_of_words] => 10407 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/161/05161102.pdf [firstpage_image] =>[orig_patent_app_number] => 311021 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/311021
Computer interface for the configuration of computer system and circuit boards Feb 12, 1989 Issued
07/307486 MULTIPLE FILE SYSTEM HAVING A PLURALITY OF FILE UNITS HOLDING THE SAME FILES Feb 7, 1989 Abandoned
Array ( [id] => 2891933 [patent_doc_number] => 05119487 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-02 [patent_title] => 'DMA controller having programmable logic array for outputting control information required during a next transfer cycle during one transfer cycle' [patent_app_type] => 1 [patent_app_number] => 7/306952 [patent_app_country] => US [patent_app_date] => 1989-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5607 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/119/05119487.pdf [firstpage_image] =>[orig_patent_app_number] => 306952 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/306952
DMA controller having programmable logic array for outputting control information required during a next transfer cycle during one transfer cycle Feb 6, 1989 Issued
Array ( [id] => 2939871 [patent_doc_number] => 05187795 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-16 [patent_title] => 'Pipelined signal processor having a plurality of bidirectional configurable parallel ports that are configurable as individual ports or as coupled pair of ports' [patent_app_type] => 1 [patent_app_number] => 7/303790 [patent_app_country] => US [patent_app_date] => 1989-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 13292 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 355 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/187/05187795.pdf [firstpage_image] =>[orig_patent_app_number] => 303790 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/303790
Pipelined signal processor having a plurality of bidirectional configurable parallel ports that are configurable as individual ports or as coupled pair of ports Jan 26, 1989 Issued
Array ( [id] => 2790154 [patent_doc_number] => 05088036 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-02-11 [patent_title] => 'Real time, concurrent garbage collection system and method' [patent_app_type] => 1 [patent_app_number] => 7/297845 [patent_app_country] => US [patent_app_date] => 1989-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 8663 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/088/05088036.pdf [firstpage_image] =>[orig_patent_app_number] => 297845 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/297845
Real time, concurrent garbage collection system and method Jan 16, 1989 Issued
Array ( [id] => 2826309 [patent_doc_number] => 05123095 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-16 [patent_title] => 'Integrated scalar and vector processors with vector addressing by the scalar processor' [patent_app_type] => 1 [patent_app_number] => 7/297981 [patent_app_country] => US [patent_app_date] => 1989-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 7611 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/123/05123095.pdf [firstpage_image] =>[orig_patent_app_number] => 297981 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/297981
Integrated scalar and vector processors with vector addressing by the scalar processor Jan 16, 1989 Issued
Array ( [id] => 2782866 [patent_doc_number] => 05075841 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-24 [patent_title] => 'Printer control with automatic intialization of stored control data' [patent_app_type] => 1 [patent_app_number] => 7/296716 [patent_app_country] => US [patent_app_date] => 1989-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3272 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 339 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/075/05075841.pdf [firstpage_image] =>[orig_patent_app_number] => 296716 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/296716
Printer control with automatic intialization of stored control data Jan 12, 1989 Issued
Array ( [id] => 2800116 [patent_doc_number] => 05101490 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-31 [patent_title] => 'Peripheral device controller with an EEPROM with microinstructions for a RAM control store' [patent_app_type] => 1 [patent_app_number] => 7/295318 [patent_app_country] => US [patent_app_date] => 1989-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3251 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/101/05101490.pdf [firstpage_image] =>[orig_patent_app_number] => 295318 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/295318
Peripheral device controller with an EEPROM with microinstructions for a RAM control store Jan 9, 1989 Issued
Array ( [id] => 2769032 [patent_doc_number] => 05060136 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-22 [patent_title] => 'Four-way associative cache with DLAT and separately addressable arrays used for updating certain bits without reading them out first' [patent_app_type] => 1 [patent_app_number] => 7/293913 [patent_app_country] => US [patent_app_date] => 1989-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3313 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/060/05060136.pdf [firstpage_image] =>[orig_patent_app_number] => 293913 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/293913
Four-way associative cache with DLAT and separately addressable arrays used for updating certain bits without reading them out first Jan 5, 1989 Issued
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