Search

Gerald Mcclain

Examiner (ID: 7690, Phone: (571)272-7803 , Office: P/3652 )

Most Active Art Unit
3652
Art Unit(s)
3653, 3652
Total Applications
1263
Issued Applications
964
Pending Applications
88
Abandoned Applications
234

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8882608 [patent_doc_number] => 20130155792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-20 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING DATA TERMINAL SUPPLIED WITH PLURAL WRITE DATA IN SERIAL' [patent_app_type] => utility [patent_app_number] => 13/715995 [patent_app_country] => US [patent_app_date] => 2012-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10101 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13715995 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/715995
Semiconductor device having data terminal supplied with plural write data in serial Dec 13, 2012 Issued
Array ( [id] => 8882614 [patent_doc_number] => 20130155798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-20 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/714015 [patent_app_country] => US [patent_app_date] => 2012-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8199 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13714015 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/714015
Semiconductor device having hierarchical bit line structure Dec 12, 2012 Issued
Array ( [id] => 10833112 [patent_doc_number] => 08861291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-14 [patent_title] => 'Memory apparatus and signal delay circuit for generating delayed column select signal' [patent_app_type] => utility [patent_app_number] => 13/711627 [patent_app_country] => US [patent_app_date] => 2012-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3515 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13711627 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/711627
Memory apparatus and signal delay circuit for generating delayed column select signal Dec 11, 2012 Issued
Array ( [id] => 8780176 [patent_doc_number] => 20130102151 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-25 [patent_title] => 'METHODS OF MANUFACTURING NAND FLASH MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 13/709131 [patent_app_country] => US [patent_app_date] => 2012-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8861 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13709131 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/709131
Methods of manufacturing NAND flash memory devices Dec 9, 2012 Issued
Array ( [id] => 9536220 [patent_doc_number] => 20140160866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-12 [patent_title] => 'APPLICATIONS FOR INTER-WORD-LINE PROGRAMMING' [patent_app_type] => utility [patent_app_number] => 13/709303 [patent_app_country] => US [patent_app_date] => 2012-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7570 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13709303 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/709303
Applications for inter-word-line programming Dec 9, 2012 Issued
Array ( [id] => 9851661 [patent_doc_number] => 08953401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-10 [patent_title] => 'Memory device and method for driving memory array thereof' [patent_app_type] => utility [patent_app_number] => 13/707611 [patent_app_country] => US [patent_app_date] => 2012-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3229 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13707611 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/707611
Memory device and method for driving memory array thereof Dec 6, 2012 Issued
Array ( [id] => 9180199 [patent_doc_number] => 20130322184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-05 [patent_title] => 'SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/706701 [patent_app_country] => US [patent_app_date] => 2012-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3247 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13706701 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/706701
Semiconductor device and operating method thereof Dec 5, 2012 Issued
Array ( [id] => 8852286 [patent_doc_number] => 20130141961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-06 [patent_title] => 'STORAGE DEVICE AND DRIVING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/690483 [patent_app_country] => US [patent_app_date] => 2012-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 17761 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13690483 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/690483
Storage device and driving method thereof Nov 29, 2012 Issued
Array ( [id] => 9510108 [patent_doc_number] => 20140146599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-29 [patent_title] => 'MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM) DIFFERENTIAL BIT CELL AND METHOD OF USE' [patent_app_type] => utility [patent_app_number] => 13/689105 [patent_app_country] => US [patent_app_date] => 2012-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6231 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13689105 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/689105
Magnetoresistive random access memory (MRAM) differential bit cell and method of use Nov 28, 2012 Issued
Array ( [id] => 10053286 [patent_doc_number] => 09093167 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-28 [patent_title] => 'Oscillator circuit with location-based charge pump enable and semiconductor memory including the same' [patent_app_type] => utility [patent_app_number] => 13/685493 [patent_app_country] => US [patent_app_date] => 2012-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3393 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13685493 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/685493
Oscillator circuit with location-based charge pump enable and semiconductor memory including the same Nov 25, 2012 Issued
Array ( [id] => 9959602 [patent_doc_number] => 09007816 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-14 [patent_title] => 'Memory circuit and memory device' [patent_app_type] => utility [patent_app_number] => 13/683257 [patent_app_country] => US [patent_app_date] => 2012-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 14440 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13683257 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/683257
Memory circuit and memory device Nov 20, 2012 Issued
Array ( [id] => 9146842 [patent_doc_number] => 20130301365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-14 [patent_title] => 'DEDICATED REFERENCE VOLTAGE GENERATION CIRCUIT FOR MEMORY' [patent_app_type] => utility [patent_app_number] => 13/680059 [patent_app_country] => US [patent_app_date] => 2012-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1145 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13680059 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/680059
DEDICATED REFERENCE VOLTAGE GENERATION CIRCUIT FOR MEMORY Nov 17, 2012 Abandoned
Array ( [id] => 9924673 [patent_doc_number] => 08982647 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-17 [patent_title] => 'Resistive random access memory equalization and sensing' [patent_app_type] => utility [patent_app_number] => 13/676943 [patent_app_country] => US [patent_app_date] => 2012-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 12087 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13676943 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/676943
Resistive random access memory equalization and sensing Nov 13, 2012 Issued
Array ( [id] => 10852603 [patent_doc_number] => 08879298 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-04 [patent_title] => 'E-fuse array circuit' [patent_app_type] => utility [patent_app_number] => 13/672299 [patent_app_country] => US [patent_app_date] => 2012-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3738 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13672299 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/672299
E-fuse array circuit Nov 7, 2012 Issued
Array ( [id] => 10035498 [patent_doc_number] => 09076824 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-07 [patent_title] => 'Memory arrays with a memory cell adjacent to a smaller size of a pillar having a greater channel length than a memory cell adjacent to a larger size of the pillar and methods' [patent_app_type] => utility [patent_app_number] => 13/667649 [patent_app_country] => US [patent_app_date] => 2012-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 10220 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13667649 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/667649
Memory arrays with a memory cell adjacent to a smaller size of a pillar having a greater channel length than a memory cell adjacent to a larger size of the pillar and methods Nov 1, 2012 Issued
Array ( [id] => 9447945 [patent_doc_number] => 20140119114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-01 [patent_title] => 'CENTER READ REFERENCE VOLTAGE DETERMINATION BASED ON ESTIMATED PROBABILITY DENSITY FUNCTION' [patent_app_type] => utility [patent_app_number] => 13/664807 [patent_app_country] => US [patent_app_date] => 2012-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7726 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13664807 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/664807
Center read reference voltage determination based on estimated probability density function Oct 30, 2012 Issued
Array ( [id] => 9447931 [patent_doc_number] => 20140119100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-01 [patent_title] => 'SRAM WITH IMPROVED WRITE OPERATION' [patent_app_type] => utility [patent_app_number] => 13/661861 [patent_app_country] => US [patent_app_date] => 2012-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4347 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13661861 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/661861
SRAM with improved write operation Oct 25, 2012 Issued
Array ( [id] => 9851646 [patent_doc_number] => 08953386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-10 [patent_title] => 'Dynamic bit line bias for programming non-volatile memory' [patent_app_type] => utility [patent_app_number] => 13/660203 [patent_app_country] => US [patent_app_date] => 2012-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 47 [patent_no_of_words] => 17858 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13660203 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/660203
Dynamic bit line bias for programming non-volatile memory Oct 24, 2012 Issued
Array ( [id] => 8813300 [patent_doc_number] => 20130114345 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-09 [patent_title] => 'NONVOLATILE MEMORY DEVICE AND DRIVING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/654973 [patent_app_country] => US [patent_app_date] => 2012-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 42 [patent_no_of_words] => 20111 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13654973 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/654973
Nonvolatile memory device and driving method thereof Oct 17, 2012 Issued
Array ( [id] => 8658312 [patent_doc_number] => 20130039141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-14 [patent_title] => 'APPARATUS, SYSTEM, AND METHOD FOR POWER REDUCTION MANAGEMENT IN A STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 13/652427 [patent_app_country] => US [patent_app_date] => 2012-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 32003 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13652427 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/652427
Apparatus, system, and method for power reduction management in a storage device Oct 14, 2012 Issued
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