Gerald Mcclain

Array ( [id] => 8365109 [patent_doc_number] => 08254179 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-28 [patent_title] => 'Method of programming a flash memory device' [patent_app_type] => utility [patent_app_number] => 13/008181 [patent_app_country] => US [patent_app_date] => 2011-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8694 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13008181 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8785915 [patent_doc_number] => 08432767 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-30 [patent_title] => 'Clock mode determination in a memory system' [patent_app_type] => utility [patent_app_number] => 13/006005 [patent_app_country] => US [patent_app_date] => 2011-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 13951 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13006005 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5949373 [patent_doc_number] => 20110107290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-05 [patent_title] => 'VARIABLE SIZED SOFT MEMORY MACROS IN STRUCTURED CELL ARRAYS, AND RELATED METHODS' [patent_app_type] => utility [patent_app_number] => 13/004587 [patent_app_country] => US [patent_app_date] => 2011-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4369 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20110107290.pdf [firstpage_image] =>[orig_patent_app_number] => 13004587 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5942527 [patent_doc_number] => 20110103147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-05 [patent_title] => 'NAND FLASH MEMORY DEVICES HAVING WIRING WITH INTEGRALLY-FORMED CONTACT PADS AND DUMMY LINES AND METHODS OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/987795 [patent_app_country] => US [patent_app_date] => 2011-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8836 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20110103147.pdf [firstpage_image] =>[orig_patent_app_number] => 12987795 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9114609 [patent_doc_number] => 08570794 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-29 [patent_title] => 'Semiconductor memory apparatus' [patent_app_type] => utility [patent_app_number] => 12/982961 [patent_app_country] => US [patent_app_date] => 2010-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 5389 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12982961 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5983251 [patent_doc_number] => 20110096608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-28 [patent_title] => 'MITIGATION OF RUNAWAY PROGRAMMING OF A MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/981842 [patent_app_country] => US [patent_app_date] => 2010-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4349 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20110096608.pdf [firstpage_image] =>[orig_patent_app_number] => 12981842 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8644185 [patent_doc_number] => 08369179 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-05 [patent_title] => 'Semiconductor module including module control circuit and method for controlling the same' [patent_app_type] => utility [patent_app_number] => 12/981815 [patent_app_country] => US [patent_app_date] => 2010-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3861 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12981815 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7764842 [patent_doc_number] => 20120033498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-09 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD OF READING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/982185 [patent_app_country] => US [patent_app_date] => 2010-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5531 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20120033498.pdf [firstpage_image] =>[orig_patent_app_number] => 12982185 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6157344 [patent_doc_number] => 20110157979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-30 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE, METHOD OF MANUFACTURING THE SAME, AND CELL ARRAY OF SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/980541 [patent_app_country] => US [patent_app_date] => 2010-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2852 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20110157979.pdf [firstpage_image] =>[orig_patent_app_number] => 12980541 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8835895 [patent_doc_number] => 08451660 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-28 [patent_title] => 'Semiconductor memory device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/978865 [patent_app_country] => US [patent_app_date] => 2010-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 9187 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 364 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12978865 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8622356 [patent_doc_number] => 08355272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-15 [patent_title] => 'Memory array having local source lines' [patent_app_type] => utility [patent_app_number] => 12/975519 [patent_app_country] => US [patent_app_date] => 2010-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6212 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12975519 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6108521 [patent_doc_number] => 20110188292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-04 [patent_title] => 'VARIABLE RESISTANCE MEMORY, OPERATING METHOD AND SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/972945 [patent_app_country] => US [patent_app_date] => 2010-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 10849 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20110188292.pdf [firstpage_image] =>[orig_patent_app_number] => 12972945 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7708891 [patent_doc_number] => 20120002492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-05 [patent_title] => 'DATA TRANSFER CIRCUIT OF SEMICONDUCTOR APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/970495 [patent_app_country] => US [patent_app_date] => 2010-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3289 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12970495 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8092751 [patent_doc_number] => 20120081984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-05 [patent_title] => 'THREE-DIMENSIONAL STACKED SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/970907 [patent_app_country] => US [patent_app_date] => 2010-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3653 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20120081984.pdf [firstpage_image] =>[orig_patent_app_number] => 12970907 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6123412 [patent_doc_number] => 20110085375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-14 [patent_title] => 'METHODS FOR DETERMINING RESISTANCE OF PHASE CHANGE MEMORY ELEMENTS' [patent_app_type] => utility [patent_app_number] => 12/969364 [patent_app_country] => US [patent_app_date] => 2010-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5174 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20110085375.pdf [firstpage_image] =>[orig_patent_app_number] => 12969364 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6037692 [patent_doc_number] => 20110090741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-21 [patent_title] => 'NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE ADAPTED TO STORE A MULTI-VALUED DATA IN A SINGLE MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 12/967227 [patent_app_country] => US [patent_app_date] => 2010-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 15408 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20110090741.pdf [firstpage_image] =>[orig_patent_app_number] => 12967227 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8702736 [patent_doc_number] => 08395963 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-12 [patent_title] => 'Data security for dynamic random access memory at power-up' [patent_app_type] => utility [patent_app_number] => 12/963965 [patent_app_country] => US [patent_app_date] => 2010-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3098 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12963965 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5957730 [patent_doc_number] => 20110182117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-28 [patent_title] => 'METHOD OF PROGRAMMING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/961133 [patent_app_country] => US [patent_app_date] => 2010-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9676 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20110182117.pdf [firstpage_image] =>[orig_patent_app_number] => 12961133 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4631956 [patent_doc_number] => 08010866 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-30 [patent_title] => 'Memory system and method using stacked memory device dice, and system using the memory system' [patent_app_type] => utility [patent_app_number] => 12/961291 [patent_app_country] => US [patent_app_date] => 2010-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5715 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/010/08010866.pdf [firstpage_image] =>[orig_patent_app_number] => 12961291 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6029381 [patent_doc_number] => 20110080767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-07 [patent_title] => 'Integrated circuit including four layers of vertically stacked\nembedded re-writeable non-volatile two-terminal memory' [patent_app_type] => utility [patent_app_number] => 12/928239 [patent_app_country] => US [patent_app_date] => 2010-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8250 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20110080767.pdf [firstpage_image] =>[orig_patent_app_number] => 12928239 [rel_patent_id] =>[rel_patent_doc_number] =>)