Search

Gerald Mcclain

Examiner (ID: 7690, Phone: (571)272-7803 , Office: P/3652 )

Most Active Art Unit
3652
Art Unit(s)
3653, 3652
Total Applications
1263
Issued Applications
964
Pending Applications
88
Abandoned Applications
234

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7802279 [patent_doc_number] => 08130555 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-06 [patent_title] => 'Nonvolatile semiconductor storage device and method of erase verifying the same' [patent_app_type] => utility [patent_app_number] => 12/493609 [patent_app_country] => US [patent_app_date] => 2009-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4097 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/130/08130555.pdf [firstpage_image] =>[orig_patent_app_number] => 12493609 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/493609
Nonvolatile semiconductor storage device and method of erase verifying the same Jun 28, 2009 Issued
Array ( [id] => 6571440 [patent_doc_number] => 20100290298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-18 [patent_title] => 'FUSE CIRCUIT AND REDUNDANCY CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/492973 [patent_app_country] => US [patent_app_date] => 2009-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6741 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0290/20100290298.pdf [firstpage_image] =>[orig_patent_app_number] => 12492973 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/492973
Fuse circuit and redundancy circuit Jun 25, 2009 Issued
Array ( [id] => 7546727 [patent_doc_number] => 08054704 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-08 [patent_title] => 'Semiconductor memory device having a redundancy memory cell array' [patent_app_type] => utility [patent_app_number] => 12/490881 [patent_app_country] => US [patent_app_date] => 2009-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3534 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/054/08054704.pdf [firstpage_image] =>[orig_patent_app_number] => 12490881 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/490881
Semiconductor memory device having a redundancy memory cell array Jun 23, 2009 Issued
Array ( [id] => 5396405 [patent_doc_number] => 20090316468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-24 [patent_title] => 'LARGE ARRAY OF UPWARD POINTING P-I-N DIODES HAVING LARGE AND UNIFORM CURRENT' [patent_app_type] => utility [patent_app_number] => 12/478481 [patent_app_country] => US [patent_app_date] => 2009-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7528 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0316/20090316468.pdf [firstpage_image] =>[orig_patent_app_number] => 12478481 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/478481
Large array of upward pointing p-i-n diodes having large and uniform current Jun 3, 2009 Issued
Array ( [id] => 134062 [patent_doc_number] => 07701773 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-20 [patent_title] => 'Nonvolatile semiconductor storage device and operation method thereof' [patent_app_type] => utility [patent_app_number] => 12/467348 [patent_app_country] => US [patent_app_date] => 2009-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 37 [patent_no_of_words] => 13715 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/701/07701773.pdf [firstpage_image] =>[orig_patent_app_number] => 12467348 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/467348
Nonvolatile semiconductor storage device and operation method thereof May 17, 2009 Issued
Array ( [id] => 7516672 [patent_doc_number] => 08040752 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-18 [patent_title] => 'Counter circuit, latency counter, semiconductor memory device including the same, and data processing system' [patent_app_type] => utility [patent_app_number] => 12/467657 [patent_app_country] => US [patent_app_date] => 2009-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 9194 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/040/08040752.pdf [firstpage_image] =>[orig_patent_app_number] => 12467657 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/467657
Counter circuit, latency counter, semiconductor memory device including the same, and data processing system May 17, 2009 Issued
Array ( [id] => 8010769 [patent_doc_number] => 08086802 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-27 [patent_title] => 'Instruction cache system, instruction-cache-system control method, and information processing apparatus' [patent_app_type] => utility [patent_app_number] => 12/435023 [patent_app_country] => US [patent_app_date] => 2009-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4994 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/086/08086802.pdf [firstpage_image] =>[orig_patent_app_number] => 12435023 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/435023
Instruction cache system, instruction-cache-system control method, and information processing apparatus May 3, 2009 Issued
Array ( [id] => 6462453 [patent_doc_number] => 20100281219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-04 [patent_title] => 'MANAGING CACHE LINE ALLOCATIONS FOR MULTIPLE ISSUE PROCESSORS' [patent_app_type] => utility [patent_app_number] => 12/433101 [patent_app_country] => US [patent_app_date] => 2009-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5379 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20100281219.pdf [firstpage_image] =>[orig_patent_app_number] => 12433101 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/433101
Managing cache line allocations for multiple issue processors Apr 29, 2009 Issued
Array ( [id] => 5491809 [patent_doc_number] => 20090292880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-26 [patent_title] => 'CACHE MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/432883 [patent_app_country] => US [patent_app_date] => 2009-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5955 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0292/20090292880.pdf [firstpage_image] =>[orig_patent_app_number] => 12432883 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/432883
Cache memory system Apr 29, 2009 Issued
Array ( [id] => 6462490 [patent_doc_number] => 20100281222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-04 [patent_title] => 'CACHE SYSTEM AND CONTROLLING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/432384 [patent_app_country] => US [patent_app_date] => 2009-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3113 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20100281222.pdf [firstpage_image] =>[orig_patent_app_number] => 12432384 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/432384
CACHE SYSTEM AND CONTROLLING METHOD THEREOF Apr 28, 2009 Abandoned
Array ( [id] => 105264 [patent_doc_number] => 07724580 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-25 [patent_title] => 'Segmented bitscan for verification of programming' [patent_app_type] => utility [patent_app_number] => 12/431573 [patent_app_country] => US [patent_app_date] => 2009-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 14333 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/724/07724580.pdf [firstpage_image] =>[orig_patent_app_number] => 12431573 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/431573
Segmented bitscan for verification of programming Apr 27, 2009 Issued
Array ( [id] => 5390342 [patent_doc_number] => 20090207655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'MULTIPLE TIME PROGRAMMABLE (MTP) PMOS FLOATING GATE-BASED NON-VOLATILE MEMORY DEVICE FOR A GENERAL PURPOSE CMOS TECHNOLOGY WITH THICK GATE OXIDE' [patent_app_type] => utility [patent_app_number] => 12/430007 [patent_app_country] => US [patent_app_date] => 2009-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5096 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20090207655.pdf [firstpage_image] =>[orig_patent_app_number] => 12430007 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/430007
Multiple time programmable (MTP) PMOS floating gate-based non-volatile memory device for a general purpose CMOS technology with thick gate oxide Apr 23, 2009 Issued
Array ( [id] => 6240829 [patent_doc_number] => 20100268888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'PROCESSING A DATA STREAM BY ACCESSING ONE OR MORE HARDWARE REGISTERS' [patent_app_type] => utility [patent_app_number] => 12/424829 [patent_app_country] => US [patent_app_date] => 2009-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5875 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20100268888.pdf [firstpage_image] =>[orig_patent_app_number] => 12424829 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/424829
Processing a data stream by accessing one or more hardware registers Apr 15, 2009 Issued
Array ( [id] => 6240826 [patent_doc_number] => 20100268886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'SPECIFYING AN ACCESS HINT FOR PREFETCHING PARTIAL CACHE BLOCK DATA IN A CACHE HIERARCHY' [patent_app_type] => utility [patent_app_number] => 12/424716 [patent_app_country] => US [patent_app_date] => 2009-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4012 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20100268886.pdf [firstpage_image] =>[orig_patent_app_number] => 12424716 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/424716
Specifying an access hint for prefetching partial cache block data in a cache hierarchy Apr 15, 2009 Issued
Array ( [id] => 157650 [patent_doc_number] => 07685364 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-23 [patent_title] => 'Memory system topologies including a buffer device and an integrated circuit memory device' [patent_app_type] => utility [patent_app_number] => 12/424442 [patent_app_country] => US [patent_app_date] => 2009-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 61 [patent_no_of_words] => 28124 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/685/07685364.pdf [firstpage_image] =>[orig_patent_app_number] => 12424442 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/424442
Memory system topologies including a buffer device and an integrated circuit memory device Apr 14, 2009 Issued
Array ( [id] => 6240814 [patent_doc_number] => 20100268883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'Information Handling System with Immediate Scheduling of Load Operations and Fine-Grained Access to Cache Memory' [patent_app_type] => utility [patent_app_number] => 12/424332 [patent_app_country] => US [patent_app_date] => 2009-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 14093 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20100268883.pdf [firstpage_image] =>[orig_patent_app_number] => 12424332 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/424332
Information handling system with immediate scheduling of load operations and fine-grained access to cache memory Apr 14, 2009 Issued
Array ( [id] => 6240816 [patent_doc_number] => 20100268884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'Updating Partial Cache Lines in a Data Processing System' [patent_app_type] => utility [patent_app_number] => 12/424434 [patent_app_country] => US [patent_app_date] => 2009-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6720 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20100268884.pdf [firstpage_image] =>[orig_patent_app_number] => 12424434 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/424434
Updating partial cache lines in a data processing system Apr 14, 2009 Issued
Array ( [id] => 186787 [patent_doc_number] => 07649778 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-19 [patent_title] => 'Method for accessing in reading, writing and programming to a NAND non-volatile memory electronic device monolithically integrated on semiconductor' [patent_app_type] => utility [patent_app_number] => 12/409740 [patent_app_country] => US [patent_app_date] => 2009-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6908 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/649/07649778.pdf [firstpage_image] =>[orig_patent_app_number] => 12409740 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/409740
Method for accessing in reading, writing and programming to a NAND non-volatile memory electronic device monolithically integrated on semiconductor Mar 23, 2009 Issued
Array ( [id] => 6374875 [patent_doc_number] => 20100315886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-16 [patent_title] => 'DATA TRANSFER APPARATUS, AND METHOD, AND SEMICONDUCTOR CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/866225 [patent_app_country] => US [patent_app_date] => 2009-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 17398 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20100315886.pdf [firstpage_image] =>[orig_patent_app_number] => 12866225 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/866225
Data transfer apparatus, and method, and semiconductor circuit Mar 5, 2009 Issued
Array ( [id] => 5528803 [patent_doc_number] => 20090198880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-06 [patent_title] => 'READ STROBE FEEDBACK IN A MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/394282 [patent_app_country] => US [patent_app_date] => 2009-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2772 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20090198880.pdf [firstpage_image] =>[orig_patent_app_number] => 12394282 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/394282
Read strobe feedback in a memory system Feb 26, 2009 Issued
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