
Gerald Mcclain
Examiner (ID: 7690, Phone: (571)272-7803 , Office: P/3652 )
| Most Active Art Unit | 3652 |
| Art Unit(s) | 3653, 3652 |
| Total Applications | 1263 |
| Issued Applications | 964 |
| Pending Applications | 88 |
| Abandoned Applications | 234 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6181109
[patent_doc_number] => 20110122718
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-05-26
[patent_title] => 'Low Cost Testing and Sorting for Integrated Circuits'
[patent_app_type] => utility
[patent_app_number] => 12/328675
[patent_app_country] => US
[patent_app_date] => 2008-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 8253
[patent_no_of_claims] => 49
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0122/20110122718.pdf
[firstpage_image] =>[orig_patent_app_number] => 12328675
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/328675 | Low cost testing and sorting for integrated circuits | Dec 3, 2008 | Issued |
Array
(
[id] => 7536494
[patent_doc_number] => 08050133
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-11-01
[patent_title] => 'Word line driver, method for driving the word line driver, and semiconductor memory device having the word line driver'
[patent_app_type] => utility
[patent_app_number] => 12/327541
[patent_app_country] => US
[patent_app_date] => 2008-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 13
[patent_no_of_words] => 5734
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/050/08050133.pdf
[firstpage_image] =>[orig_patent_app_number] => 12327541
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/327541 | Word line driver, method for driving the word line driver, and semiconductor memory device having the word line driver | Dec 2, 2008 | Issued |
Array
(
[id] => 7524027
[patent_doc_number] => 08027191
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-09-27
[patent_title] => 'Write circuit for providing distinctive write currents to a chalcogenide memory cell'
[patent_app_type] => utility
[patent_app_number] => 12/531849
[patent_app_country] => US
[patent_app_date] => 2008-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 2305
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/027/08027191.pdf
[firstpage_image] =>[orig_patent_app_number] => 12531849
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/531849 | Write circuit for providing distinctive write currents to a chalcogenide memory cell | Nov 30, 2008 | Issued |
Array
(
[id] => 5484225
[patent_doc_number] => 20090273990
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-11-05
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/323687
[patent_app_country] => US
[patent_app_date] => 2008-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 11818
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0273/20090273990.pdf
[firstpage_image] =>[orig_patent_app_number] => 12323687
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/323687 | Semiconductor device | Nov 25, 2008 | Issued |
Array
(
[id] => 7516639
[patent_doc_number] => 08040719
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-10-18
[patent_title] => 'Nonvolatile memory devices having bit line discharge control circuits therein that provide equivalent bit line discharge control'
[patent_app_type] => utility
[patent_app_number] => 12/323583
[patent_app_country] => US
[patent_app_date] => 2008-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5137
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/040/08040719.pdf
[firstpage_image] =>[orig_patent_app_number] => 12323583
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/323583 | Nonvolatile memory devices having bit line discharge control circuits therein that provide equivalent bit line discharge control | Nov 25, 2008 | Issued |
Array
(
[id] => 5532127
[patent_doc_number] => 20090231915
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-09-17
[patent_title] => 'Reading array cell with matched reference cell'
[patent_app_type] => utility
[patent_app_number] => 12/292654
[patent_app_country] => US
[patent_app_date] => 2008-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3530
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0231/20090231915.pdf
[firstpage_image] =>[orig_patent_app_number] => 12292654
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/292654 | Reading array cell with matched reference cell | Nov 23, 2008 | Issued |
Array
(
[id] => 5562793
[patent_doc_number] => 20090135645
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-05-28
[patent_title] => 'Data Programming Circuits And Memory Programming Methods'
[patent_app_type] => utility
[patent_app_number] => 12/275223
[patent_app_country] => US
[patent_app_date] => 2008-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 3926
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0135/20090135645.pdf
[firstpage_image] =>[orig_patent_app_number] => 12275223
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/275223 | Data programming circuits and memory programming methods | Nov 20, 2008 | Issued |
Array
(
[id] => 6564538
[patent_doc_number] => 20100128521
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-05-27
[patent_title] => 'APPLYING NEGATIVE GATE VOLTAGE TO WORDLINES ADJACENT TO WORDLINE ASSOCIATED WITH READ OR VERIFY TO REDUCE ADJACENT WORDLINE DISTURB'
[patent_app_type] => utility
[patent_app_number] => 12/275663
[patent_app_country] => US
[patent_app_date] => 2008-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 12653
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0128/20100128521.pdf
[firstpage_image] =>[orig_patent_app_number] => 12275663
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/275663 | Applying negative gate voltage to wordlines adjacent to wordline associated with read or verify to reduce adjacent wordline disturb | Nov 20, 2008 | Issued |
Array
(
[id] => 6530102
[patent_doc_number] => 20100124095
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-05-20
[patent_title] => 'Floating Source Line Architecture for Non-Volatile Memory'
[patent_app_type] => utility
[patent_app_number] => 12/272507
[patent_app_country] => US
[patent_app_date] => 2008-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4076
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0124/20100124095.pdf
[firstpage_image] =>[orig_patent_app_number] => 12272507
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/272507 | Floating source line architecture for non-volatile memory | Nov 16, 2008 | Issued |
Array
(
[id] => 6276785
[patent_doc_number] => 20100118637
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-05-13
[patent_title] => 'Circuts and methods for reducing minimum supply for register file cells'
[patent_app_type] => utility
[patent_app_number] => 12/291433
[patent_app_country] => US
[patent_app_date] => 2008-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2568
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0118/20100118637.pdf
[firstpage_image] =>[orig_patent_app_number] => 12291433
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/291433 | Circuits and methods for reducing minimum supply for register file cells | Nov 9, 2008 | Issued |
Array
(
[id] => 5408700
[patent_doc_number] => 20090122598
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-05-14
[patent_title] => 'RESISTANCE CHANGE MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/266879
[patent_app_country] => US
[patent_app_date] => 2008-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5237
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0122/20090122598.pdf
[firstpage_image] =>[orig_patent_app_number] => 12266879
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/266879 | Resistance change memory device | Nov 6, 2008 | Issued |
Array
(
[id] => 7765431
[patent_doc_number] => 08116115
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-02-14
[patent_title] => 'Multilevel phase change memory operation'
[patent_app_type] => utility
[patent_app_number] => 12/266447
[patent_app_country] => US
[patent_app_date] => 2008-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 8150
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/116/08116115.pdf
[firstpage_image] =>[orig_patent_app_number] => 12266447
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/266447 | Multilevel phase change memory operation | Nov 5, 2008 | Issued |
Array
(
[id] => 7777227
[patent_doc_number] => 08120940
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-02-21
[patent_title] => 'Programmable resistance memory'
[patent_app_type] => utility
[patent_app_number] => 12/291111
[patent_app_country] => US
[patent_app_date] => 2008-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 12580
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/120/08120940.pdf
[firstpage_image] =>[orig_patent_app_number] => 12291111
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/291111 | Programmable resistance memory | Nov 5, 2008 | Issued |
Array
(
[id] => 8399868
[patent_doc_number] => 08270246
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-09-18
[patent_title] => 'Optimized selection of memory chips in multi-chips memory devices'
[patent_app_type] => utility
[patent_app_number] => 12/680901
[patent_app_country] => US
[patent_app_date] => 2008-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 5552
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12680901
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/680901 | Optimized selection of memory chips in multi-chips memory devices | Nov 3, 2008 | Issued |
Array
(
[id] => 5445281
[patent_doc_number] => 20090046507
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-02-19
[patent_title] => 'REDUCING EFFECTS OF PROGRAM DISTURB IN A MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/257732
[patent_app_country] => US
[patent_app_date] => 2008-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4096
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0046/20090046507.pdf
[firstpage_image] =>[orig_patent_app_number] => 12257732
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/257732 | Reducing effects of program disturb in a memory device | Oct 23, 2008 | Issued |
Array
(
[id] => 240565
[patent_doc_number] => 07593287
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-09-22
[patent_title] => 'READ command triggered synchronization circuitry'
[patent_app_type] => utility
[patent_app_number] => 12/249689
[patent_app_country] => US
[patent_app_date] => 2008-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3123
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/593/07593287.pdf
[firstpage_image] =>[orig_patent_app_number] => 12249689
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/249689 | READ command triggered synchronization circuitry | Oct 9, 2008 | Issued |
Array
(
[id] => 5440340
[patent_doc_number] => 20090091979
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-09
[patent_title] => 'RELIABLE DATA STORAGE IN ANALOG MEMORY CELLS IN THE PRESENCE OF TEMPERATURE VARIATIONS'
[patent_app_type] => utility
[patent_app_number] => 12/245749
[patent_app_country] => US
[patent_app_date] => 2008-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 6505
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0091/20090091979.pdf
[firstpage_image] =>[orig_patent_app_number] => 12245749
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/245749 | Reliable data storage in analog memory cells in the presence of temperature variations | Oct 4, 2008 | Issued |
Array
(
[id] => 5283635
[patent_doc_number] => 20090097309
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-16
[patent_title] => 'NONVOLATILE SEMICONDUCTOR STORAGE DEVICE, AND METHOD FOR CONTROLLING NONVOLATILE SEMICONDUCTOR STORAGE DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/244307
[patent_app_country] => US
[patent_app_date] => 2008-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 9350
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0097/20090097309.pdf
[firstpage_image] =>[orig_patent_app_number] => 12244307
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/244307 | Nonvolatile semiconductor storage device, and method for controlling nonvolatile semiconductor storage device | Oct 1, 2008 | Issued |
Array
(
[id] => 6368303
[patent_doc_number] => 20100080075
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-04-01
[patent_title] => 'Memory Device Refresh Method and Apparatus'
[patent_app_type] => utility
[patent_app_number] => 12/240331
[patent_app_country] => US
[patent_app_date] => 2008-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3870
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0080/20100080075.pdf
[firstpage_image] =>[orig_patent_app_number] => 12240331
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/240331 | Memory device refresh method and apparatus | Sep 28, 2008 | Issued |
Array
(
[id] => 4492403
[patent_doc_number] => 07885114
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-02-08
[patent_title] => 'NAND flash memory devices having wiring with integrally-formed contact pads and dummy lines and methods of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 12/240529
[patent_app_country] => US
[patent_app_date] => 2008-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 16
[patent_no_of_words] => 8818
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/885/07885114.pdf
[firstpage_image] =>[orig_patent_app_number] => 12240529
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/240529 | NAND flash memory devices having wiring with integrally-formed contact pads and dummy lines and methods of manufacturing the same | Sep 28, 2008 | Issued |