
Gerald Mcclain
Examiner (ID: 7690, Phone: (571)272-7803 , Office: P/3652 )
| Most Active Art Unit | 3652 |
| Art Unit(s) | 3653, 3652 |
| Total Applications | 1263 |
| Issued Applications | 964 |
| Pending Applications | 88 |
| Abandoned Applications | 234 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4730340
[patent_doc_number] => 20080209121
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-08-28
[patent_title] => 'Serial Content Addressable Memory'
[patent_app_type] => utility
[patent_app_number] => 12/113242
[patent_app_country] => US
[patent_app_date] => 2008-05-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 3823
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0209/20080209121.pdf
[firstpage_image] =>[orig_patent_app_number] => 12113242
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/113242 | Serial content addressable memory | Apr 30, 2008 | Issued |
Array
(
[id] => 4717336
[patent_doc_number] => 20080239858
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-02
[patent_title] => 'INTERFACE CIRCUIT SYSTEM AND METHOD FOR AUTONOMOUSLY PERFORMING POWER MANAGEMENT OPERATIONS IN CONJUNCTION WITH A PLURALITY OF MEMORY CIRCUITS'
[patent_app_type] => utility
[patent_app_number] => 12/111828
[patent_app_country] => US
[patent_app_date] => 2008-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 17655
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0239/20080239858.pdf
[firstpage_image] =>[orig_patent_app_number] => 12111828
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/111828 | Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits | Apr 28, 2008 | Issued |
Array
(
[id] => 4717335
[patent_doc_number] => 20080239857
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-02
[patent_title] => 'INTERFACE CIRCUIT SYSTEM AND METHOD FOR PERFORMING POWER MANAGEMENT OPERATIONS IN CONJUNCTION WITH ONLY A PORTION OF A MEMORY CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 12/111819
[patent_app_country] => US
[patent_app_date] => 2008-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 17649
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0239/20080239857.pdf
[firstpage_image] =>[orig_patent_app_number] => 12111819
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/111819 | Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit | Apr 28, 2008 | Issued |
Array
(
[id] => 4958941
[patent_doc_number] => 20080273365
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-11-06
[patent_title] => 'NONVOLATILE MEMORY DEVICE HAVING TWIN MEMORY CELLS'
[patent_app_type] => utility
[patent_app_number] => 12/107985
[patent_app_country] => US
[patent_app_date] => 2008-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7712
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0273/20080273365.pdf
[firstpage_image] =>[orig_patent_app_number] => 12107985
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/107985 | Nonvolatile memory device having twin memory cells | Apr 22, 2008 | Issued |
Array
(
[id] => 26188
[patent_doc_number] => 07796447
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-09-14
[patent_title] => 'Semiconductor memory device having output impedance adjustment circuit and test method of output impedance'
[patent_app_type] => utility
[patent_app_number] => 12/107945
[patent_app_country] => US
[patent_app_date] => 2008-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 8604
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 217
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/796/07796447.pdf
[firstpage_image] =>[orig_patent_app_number] => 12107945
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/107945 | Semiconductor memory device having output impedance adjustment circuit and test method of output impedance | Apr 22, 2008 | Issued |
Array
(
[id] => 4811907
[patent_doc_number] => 20080192538
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-08-14
[patent_title] => 'ARCHITECTURE AND METHOD FOR NAND FLASH MEMORY'
[patent_app_type] => utility
[patent_app_number] => 12/107315
[patent_app_country] => US
[patent_app_date] => 2008-04-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2734
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0192/20080192538.pdf
[firstpage_image] =>[orig_patent_app_number] => 12107315
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/107315 | Architecture and method for NAND flash memory | Apr 21, 2008 | Issued |
Array
(
[id] => 4790756
[patent_doc_number] => 20080291729
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-11-27
[patent_title] => 'Non-Volatile Memory With High Reliability'
[patent_app_type] => utility
[patent_app_number] => 12/106777
[patent_app_country] => US
[patent_app_date] => 2008-04-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4556
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0291/20080291729.pdf
[firstpage_image] =>[orig_patent_app_number] => 12106777
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/106777 | Non-volatile memory with high reliability | Apr 20, 2008 | Issued |
Array
(
[id] => 4584758
[patent_doc_number] => 07826299
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-11-02
[patent_title] => 'Method and apparatus for operating maskable memory cells'
[patent_app_type] => utility
[patent_app_number] => 12/106931
[patent_app_country] => US
[patent_app_date] => 2008-04-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 7238
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/826/07826299.pdf
[firstpage_image] =>[orig_patent_app_number] => 12106931
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/106931 | Method and apparatus for operating maskable memory cells | Apr 20, 2008 | Issued |
Array
(
[id] => 275294
[patent_doc_number] => 07561464
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-07-14
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 12/106919
[patent_app_country] => US
[patent_app_date] => 2008-04-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 40
[patent_figures_cnt] => 55
[patent_no_of_words] => 20002
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/561/07561464.pdf
[firstpage_image] =>[orig_patent_app_number] => 12106919
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/106919 | Semiconductor memory device | Apr 20, 2008 | Issued |
Array
(
[id] => 56356
[patent_doc_number] => 07768849
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-08-03
[patent_title] => 'Semiconductor memory device capable of optimizing signal transmission power and power initializing method thereof'
[patent_app_type] => utility
[patent_app_number] => 12/106175
[patent_app_country] => US
[patent_app_date] => 2008-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 5848
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/768/07768849.pdf
[firstpage_image] =>[orig_patent_app_number] => 12106175
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/106175 | Semiconductor memory device capable of optimizing signal transmission power and power initializing method thereof | Apr 17, 2008 | Issued |
Array
(
[id] => 174803
[patent_doc_number] => 07660185
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-02-09
[patent_title] => 'Chip select controller and non-volatile memory device including the same'
[patent_app_type] => utility
[patent_app_number] => 12/102705
[patent_app_country] => US
[patent_app_date] => 2008-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4119
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/660/07660185.pdf
[firstpage_image] =>[orig_patent_app_number] => 12102705
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/102705 | Chip select controller and non-volatile memory device including the same | Apr 13, 2008 | Issued |
Array
(
[id] => 7592284
[patent_doc_number] => 07652921
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-01-26
[patent_title] => 'Multi-level non-volatile memory cell with high-VT enhanced BTBT device'
[patent_app_type] => utility
[patent_app_number] => 12/080127
[patent_app_country] => US
[patent_app_date] => 2008-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 39
[patent_no_of_words] => 8572
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/652/07652921.pdf
[firstpage_image] =>[orig_patent_app_number] => 12080127
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/080127 | Multi-level non-volatile memory cell with high-VT enhanced BTBT device | Mar 30, 2008 | Issued |
Array
(
[id] => 4615314
[patent_doc_number] => 07990761
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-08-02
[patent_title] => 'Immunity of phase change material to disturb in the amorphous phase'
[patent_app_type] => utility
[patent_app_number] => 12/080001
[patent_app_country] => US
[patent_app_date] => 2008-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 6514
[patent_no_of_claims] => 76
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 30
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/990/07990761.pdf
[firstpage_image] =>[orig_patent_app_number] => 12080001
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/080001 | Immunity of phase change material to disturb in the amorphous phase | Mar 30, 2008 | Issued |
Array
(
[id] => 4806875
[patent_doc_number] => 20080170453
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-17
[patent_title] => 'Power circuits for reducing a number of power supply voltage taps required for sensing a resistive memory'
[patent_app_type] => utility
[patent_app_number] => 12/076519
[patent_app_country] => US
[patent_app_date] => 2008-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3670
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0170/20080170453.pdf
[firstpage_image] =>[orig_patent_app_number] => 12076519
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/076519 | Power circuits for reducing a number of power supply voltage taps required for sensing a resistive memory | Mar 18, 2008 | Issued |
Array
(
[id] => 84223
[patent_doc_number] => 07746697
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-06-29
[patent_title] => 'Nonvolatile semiconductor memory'
[patent_app_type] => utility
[patent_app_number] => 12/046150
[patent_app_country] => US
[patent_app_date] => 2008-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 29
[patent_no_of_words] => 14194
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/746/07746697.pdf
[firstpage_image] =>[orig_patent_app_number] => 12046150
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/046150 | Nonvolatile semiconductor memory | Mar 10, 2008 | Issued |
Array
(
[id] => 4818340
[patent_doc_number] => 20080225599
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-18
[patent_title] => 'FLASH MEMORY DEVICE WITH REDUCED COUPLING EFFECT AMONG CELLS AND METHOD OF DRIVING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/045133
[patent_app_country] => US
[patent_app_date] => 2008-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5714
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0225/20080225599.pdf
[firstpage_image] =>[orig_patent_app_number] => 12045133
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/045133 | Flash memory device with reduced coupling effect among cells and method of driving the same | Mar 9, 2008 | Issued |
Array
(
[id] => 198890
[patent_doc_number] => 07639536
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-12-29
[patent_title] => 'Storage unit of single-conductor non-volatile memory cell and method of erasing the same'
[patent_app_type] => utility
[patent_app_number] => 12/044637
[patent_app_country] => US
[patent_app_date] => 2008-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 3300
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/639/07639536.pdf
[firstpage_image] =>[orig_patent_app_number] => 12044637
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/044637 | Storage unit of single-conductor non-volatile memory cell and method of erasing the same | Mar 6, 2008 | Issued |
Array
(
[id] => 4696897
[patent_doc_number] => 20080219081
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-11
[patent_title] => 'SEMICONDUCTOR MEMORY APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 12/044857
[patent_app_country] => US
[patent_app_date] => 2008-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3969
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0219/20080219081.pdf
[firstpage_image] =>[orig_patent_app_number] => 12044857
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/044857 | Semiconductor memory apparatus | Mar 6, 2008 | Issued |
Array
(
[id] => 115538
[patent_doc_number] => 07715233
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-05-11
[patent_title] => 'Non-volatile memory device'
[patent_app_type] => utility
[patent_app_number] => 12/044441
[patent_app_country] => US
[patent_app_date] => 2008-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 2833
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/715/07715233.pdf
[firstpage_image] =>[orig_patent_app_number] => 12044441
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/044441 | Non-volatile memory device | Mar 6, 2008 | Issued |
Array
(
[id] => 124316
[patent_doc_number] => 07710813
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-05-04
[patent_title] => 'Electronic fuse array'
[patent_app_type] => utility
[patent_app_number] => 12/043099
[patent_app_country] => US
[patent_app_date] => 2008-03-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 14
[patent_no_of_words] => 5477
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/710/07710813.pdf
[firstpage_image] =>[orig_patent_app_number] => 12043099
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/043099 | Electronic fuse array | Mar 4, 2008 | Issued |